 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| numicro? nuc100 series technical reference manual arm cortex?-m0 32-bit microcontroller publication release date: dec. 22, 2010 - 1 - revision v1.06 numicro? family nuc100 series technical reference manual the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation.
numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 2 - revision v1.06 contents 1 general des cription ....................................................................................................... 13 2 features ....................................................................................................................... ........ 14 2.1 numicro ? nuc100 features ? advanc ed line............................................................ 14 2.2 numicro ? nuc120 features ? usb line .................................................................... 18 2.3 numicro ? nuc130 features ? automotive line.......................................................... 22 2.4 numicro ? nuc140 features ? connectivity line ........................................................ 26 3 parts information list and pin conf iguration .................................................... 30 3.1 numicro ? nuc100 products selection guide ............................................................. 30 3.1.1 numicro ? nuc100 medium density adva nce line sele ction guide ............................. 30 3.1.2 numicro ? nuc100 low density advanc e line select ion guide ................................... 30 3.2 numicro ? nuc120 products selection guide ............................................................. 31 3.2.1 numicro ? nuc120 medium density u sb line select ion guide.................................... 31 3.2.2 numicro ? nuc120 low density usb line selecti on guide.......................................... 31 3.3 numicro ? nuc130 products selection guide ............................................................. 32 3.3.1 numicro ? nuc130 medium density automo tive line sele ction guide ......................... 32 3.3.2 numicro ? nuc130 low density automoti ve line select ion guide ............................... 32 3.4 numicro ? nuc140 products selection guide ............................................................. 33 3.4.1 numicro ? nuc140 medium density connec tivity line sele ction guide........................ 33 3.4.2 numicro ? nuc140 low density connecti vity line sele ction guide.............................. 33 3.5 pin config uration .......................................................................................................... 35 3.5.1 numicro ? nuc100/nuc120/nuc130/nu c140 medium densit y pin diagram ............. 35 3.5.2 numicro ? nuc100/120/130/140 low density pi n diagr am........................................... 47 3.6 pin descr iption.............................................................................................................. 55 3.6.1 numicro ? nuc100/nuc120/nuc130/nuc 140 medium density pin description......... 55 3.6.2 numicro ? nuc100/nuc120/nuc130/nu c140 low density pin descr iption ............... 83 4 block diagram .................................................................................................................. 103 4.1 numicro ? nuc100/nuc120/nuc130/ nuc140 medium density block diagram..... 103 4.1.1 numicro ? nuc100 medium density block diagr am.................................................... 103 4.1.2 numicro ? nuc120 medium density block diagr am.................................................... 104 4.1.3 numicro ? nuc130 medium density block diagr am.................................................... 105 4.1.4 numicro ? nuc140 medium density block diagr am.................................................... 106 4.2 numicro ? nuc100/nuc120/nuc 130/nuc140 low density block diagram........... 107 4.2.1 numicro ? nuc100 low densit y block diagram.......................................................... 107 4.2.2 numicro ? nuc120 low densit y block diagram.......................................................... 108 4.2.3 numicro ? nuc130 low densit y block diagram.......................................................... 109 4.2.4 numicro ? nuc140 low densit y block diagram.......................................................... 110 5 functional d escription................................................................................................ 111 5.1 arm ? cortex?- m0 core ............................................................................................ 111 5.2 system manager......................................................................................................... 113 5.2.1 overview ...................................................................................................................... 113 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 3 - revision v1.06 5.2.2 system reset ............................................................................................................... 113 5.2.3 system power distribut ion ........................................................................................... 114 5.2.4 system memory map.................................................................................................... 116 5.2.5 system manager c ontrol regi sters.............................................................................. 118 5.2.6 system timer (systick) ............................................................................................... 154 5.2.7 nested vectored interrupt controller (nvic) ................................................................ 159 5.2.8 system contro l regi ster............................................................................................... 183 5.3 clock cont roller .......................................................................................................... 191 5.3.1 overview ...................................................................................................................... 191 5.3.2 clock gene rator ........................................................................................................... 191 5.3.3 system clock & systick clock..................................................................................... 192 5.3.4 peripheral s clock ......................................................................................................... 193 5.3.5 power down mode (deep sleep mode ) clock.............................................................. 193 5.3.6 frequency divi der ou tput............................................................................................. 194 5.3.7 register map ................................................................................................................ 195 5.3.8 register de scription ..................................................................................................... 196 5.4 usb device c ontroller (usb) ..................................................................................... 215 5.4.1 overview ...................................................................................................................... 215 5.4.2 featur es ....................................................................................................................... 215 5.4.3 block di agram .............................................................................................................. 216 5.4.4 function de scription..................................................................................................... 217 5.4.5 register and me mory map ........................................................................................... 221 5.4.6 register de scription ..................................................................................................... 223 5.5 general purpose i/o................................................................................................... 240 5.5.1 overview ...................................................................................................................... 240 5.5.2 featur es ....................................................................................................................... 240 5.5.3 function de scription..................................................................................................... 241 5.5.4 register map ................................................................................................................ 243 5.5.5 register de scription ..................................................................................................... 247 5.6 i 2 c serial interface controller (master/slave) (i 2 c) .................................................... 259 5.6.1 overview ...................................................................................................................... 259 5.6.2 featur es ....................................................................................................................... 260 5.6.3 function de scription..................................................................................................... 261 5.6.4 protocol r egister s ........................................................................................................ 264 5.6.5 register map ................................................................................................................ 267 5.6.6 register de scription ..................................................................................................... 268 5.6.7 modes of o peratio n ...................................................................................................... 276 5.6.8 data transfer flow in five operat ing modes ............................................................... 277 5.7 pwm generator and capt ure timer (pwm) .............................................................. 283 5.7.1 overview ...................................................................................................................... 283 5.7.2 featur es ....................................................................................................................... 284 5.7.3 block di agram .............................................................................................................. 285 5.7.4 function de scription..................................................................................................... 289 5.7.5 register map ................................................................................................................ 296 5.7.6 register de scription ..................................................................................................... 299 5.8 real time clock (rtc)............................................................................................... 322 5.8.1 overview ...................................................................................................................... 322 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 4 - revision v1.06 5.8.2 featur es ....................................................................................................................... 322 5.8.3 block di agram .............................................................................................................. 323 5.8.4 function de scription..................................................................................................... 324 5.8.5 register map ................................................................................................................ 326 5.8.6 register de scription ..................................................................................................... 327 5.9 serial peripheral interface (spi) ................................................................................. 341 5.9.1 overview ...................................................................................................................... 341 5.9.2 featur es ....................................................................................................................... 341 5.9.3 block di agram .............................................................................................................. 342 5.9.4 function de scription..................................................................................................... 343 5.9.5 timing di agram ............................................................................................................ 350 5.9.6 programming examples ............................................................................................... 353 5.9.7 register map ................................................................................................................ 355 5.9.8 register de scription ..................................................................................................... 356 5.10 timer controll er (tmr)............................................................................................... 366 5.10.1 overview .................................................................................................................... 366 5.10.2 featur es ..................................................................................................................... 366 5.10.3 block di agram ............................................................................................................ 367 5.10.4 function de scription................................................................................................... 368 5.10.5 register map .............................................................................................................. 369 5.10.6 register de scription ................................................................................................... 370 5.11 watchdog ti mer (wdt).............................................................................................. 375 5.11.1 overview .................................................................................................................... 375 5.11.2 featur es ..................................................................................................................... 377 5.11.3 block di agram ............................................................................................................ 377 5.11.4 register map .............................................................................................................. 378 5.11.5 register de scription ................................................................................................... 379 5.12 uart interface c ontroller (uart) ............................................................................. 381 5.12.1 overview .................................................................................................................... 381 5.12.2 featur es ..................................................................................................................... 383 5.12.3 block di agram ............................................................................................................ 384 5.12.4 irda mode .................................................................................................................. 387 5.12.5 lin (local interconnec tion networ k) mode ................................................................ 389 5.12.6 rs-485 function mode (low density only)................................................................. 390 5.12.7 register map .............................................................................................................. 392 5.12.8 register de scription ................................................................................................... 394 5.13 controller area ne twork (can) .................................................................................. 419 5.13.1 overview .................................................................................................................... 419 5.13.2 featur es ..................................................................................................................... 419 5.13.3 block di agram ............................................................................................................ 420 5.13.4 functional de scription ................................................................................................ 421 5.13.5 register map .............................................................................................................. 428 5.13.6 register de scription ................................................................................................... 429 5.14 ps2 device cont roller (p s2d).................................................................................... 453 5.14.1 overview .................................................................................................................... 453 5.14.2 featur es ..................................................................................................................... 453 5.14.3 block di agram ............................................................................................................ 454 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 5 - revision v1.06 5.14.4 functional de scription ................................................................................................ 455 5.14.5 register map .............................................................................................................. 460 5.14.6 register de scription ................................................................................................... 461 5.15 i 2 s controller (i 2 s)....................................................................................................... 468 5.15.1 overview .................................................................................................................... 468 5.15.2 featur es ..................................................................................................................... 468 5.15.3 block di agram ............................................................................................................ 469 5.15.4 functional de scription ................................................................................................ 470 5.15.5 register map .............................................................................................................. 472 5.15.6 register de scription ................................................................................................... 473 5.16 analog-to-digital converter (adc) ............................................................................. 485 5.16.1 overview .................................................................................................................... 485 5.16.2 featur es ..................................................................................................................... 485 5.16.3 block di agram ............................................................................................................ 486 5.16.4 functional de scription ................................................................................................ 487 5.16.5 register map .............................................................................................................. 493 5.16.6 register de scription ................................................................................................... 494 5.17 analog comparat or (cmp) ......................................................................................... 508 5.17.1 overview .................................................................................................................... 508 5.17.2 featur es ..................................................................................................................... 508 5.17.3 block di agram ............................................................................................................ 509 5.17.4 functional de scription ................................................................................................ 510 5.17.5 register map .............................................................................................................. 511 5.17.6 register de scription ................................................................................................... 512 5.18 pdma contro ller (p dma) ........................................................................................... 515 5.18.1 overview .................................................................................................................... 515 5.18.2 featur es ..................................................................................................................... 515 5.18.3 block di agram ............................................................................................................ 516 5.18.4 function de scription................................................................................................... 518 5.18.5 register map .............................................................................................................. 519 5.18.6 register de scription ................................................................................................... 520 5.19 external bus in terface (ebi) ....................................................................................... 541 5.19.1 overview .................................................................................................................... 541 5.19.2 featur es ..................................................................................................................... 541 5.19.3 block di agram ............................................................................................................ 542 5.19.4 function de scription................................................................................................... 542 5.19.5 register map .............................................................................................................. 548 5.19.6 register de scription ................................................................................................... 548 6 flash memory co ntroller (fmc) .............................................................................. 551 6.1 overview ..................................................................................................................... 551 6.2 features...................................................................................................................... 551 6.3 block diagram............................................................................................................. 552 6.4 flash memory organization........................................................................................ 554 6.5 boot selection............................................................................................................. 557 6.6 data flash................................................................................................................... 557 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 6 - revision v1.06 6.7 user config uration...................................................................................................... 559 6.8 in system program (isp)............................................................................................ 562 6.8.1 isp proc edure .............................................................................................................. 562 6.9 flash control r egister map ........................................................................................ 565 6.10 flash control regist er description ............................................................................. 566 7 electrical cha racteristics....................................................................................... 574 7.1 absolute maxi mum ratings ........................................................................................ 574 7.2 dc electrical characteristics ...................................................................................... 575 7.2.1 numicro ? nuc100/nuc120/nuc130/nuc140 medium density dc electrical characteri stics ................................................................................................................ .......... 575 7.2.2 numicro ? nuc100/nuc120/nuc130/nuc140 low density dc electrical characteri stics ................................................................................................................ .......... 579 7.2.3 operating current curve (t est condition : run nop)..................................................... 582 7.2.4 idle current curve ........................................................................................................ 586 7.2.5 power down cu rrent curve.......................................................................................... 588 7.3 ac electrical ch aracteristics ...................................................................................... 589 7.3.1 external 4~24mhz crystal............................................................................................ 589 7.3.2 external 32.768 khz crystal ......................................................................................... 590 7.3.3 internal 22.1184 mhz osc illator ................................................................................... 590 7.3.4 internal 10 kh z oscilla tor ............................................................................................. 590 7.4 analog characteristics................................................................................................ 591 7.4.1 specification of 12-bit saradc ................................................................................... 591 7.4.2 specification of ldo & power m anagement ................................................................ 592 7.4.3 specification of lo w voltage reset .............................................................................. 593 7.4.4 specification of brownout detector............................................................................... 593 7.4.5 specification of po wer-on rese t (5v) .......................................................................... 593 7.4.6 specification of te mperature sens or ........................................................................... 593 7.4.7 specification of compar ator ......................................................................................... 594 7.4.8 specification of usb phy ............................................................................................ 595 8 package dime nsio ns ....................................................................................................... 596 8.1 100l lqfp (14x14x1.4 mm footprin t 2.0mm) ............................................................ 596 8.2 64l lqfp (10x10x1.4mm footprint 2.0 mm) .............................................................. 597 8.3 48l lqfp (7x7x1.4mm footprint 2.0mm) ................................................................... 598 9 revision histor y .............................................................................................................. 599 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 7 - revision v1.06 figures figure 3-1 numicro ? nuc100 series selecti on code ................................................................... 34 figure 3-2 numicro ? nuc100 medium density lqfp 100-pin pin diagram ............................... 35 figure 3-3 numicro ? nuc100 medium density lq fp 64-pin pi n diagram ................................. 36 figure 3-4 numicro ? nuc100 medium density lq fp 48-pin pi n diagram ................................. 37 figure 3-5 numicro ? nuc120 medium density lqfp 100-pin pin diagram ............................... 38 figure 3-6 numicro ? nuc120 medium density lq fp 64-pin pi n diagram ................................. 39 figure 3-7 numicro ? nuc120 medium density lq fp 48-pin pi n diagram ................................. 40 figure 3-8 numicro ? nuc130 medium density lqfp 100-pin pin diagram ............................... 41 figure 3-9 numicro ? nuc130 medium density lq fp 64-pin pi n diagram ................................. 42 figure 3-10 numicro ? nuc130 medium density lqfp 48-pin pin diagram ............................... 43 figure 3-11 numicro ? nuc140 medium density lq fp 100-pin pi n diagram ............................. 44 figure 3-12 numicro ? nuc140 medium density lqfp 64-pin pin diagram ............................... 45 figure 3-13 numicro ? nuc140 medium density lqfp 48-pin pin diagram ............................... 46 figure 3-14 numicro ? nuc100 low density lqfp 64-pin pin diagram...................................... 47 figure 3-15 numicro ? nuc100 low density lqfp 48-pin pin diagram...................................... 48 figure 3-16 numicro ? nuc120 low density lqfp 64-pin pin diagram...................................... 49 figure 3-17 numicro ? nuc120 low density lqfp 48-pin pin diagram...................................... 50 figure 3-18 numicro ? nuc130 low density lqfp 64-pin pin diagram...................................... 51 figure 3-19 numicro ? nuc130 low density lqfp 48-pin pin diagram...................................... 52 figure 3-20 numicro ? nuc140 low density lqfp 64-pin pin diagram...................................... 53 figure 3-21 numicro ? nuc140 low density lqfp 48-pin pin diagram...................................... 54 figure 4-1 numicro ? nuc100 medium dens ity block diagram ................................................. 103 figure 4-2 numicro ? nuc120 medium dens ity block diagram ................................................. 104 figure 4-3 numicro ? nuc130 medium dens ity block diagram ................................................. 105 figure 4-4 numicro ? nuc140 medium dens ity block diagram ................................................. 106 figure 4-5 numicro ? nuc100 low densit y block di agram ....................................................... 107 figure 4-6 numicro ? nuc120 low densit y block di agram ....................................................... 108 figure 4-7 numicro ? nuc130 low densit y block di agram ....................................................... 109 figure 4-8 numicro ? nuc140 low densit y block di agram ....................................................... 110 figure 5-1 functional controller diagram.................................................................................... 111 figure 5-2 numicro ? nuc120/nuc140 power di stribution diagram......................................... 114 figure 5-3 numicro ? nuc100/ nuc130 powe r distributi on diagram........................................ 115 figure 5-4 clock generat or block diagram................................................................................... 191 figure 5-5 system cl ock block diagram ..................................................................................... 192 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 8 - revision v1.06 figure 5-6 systick clock control blo c k diagram ........................................................................ 192 figure 5-7 clock source of frequency divider ............................................................................ 194 figure 5-8 block diagram of frequency divider .......................................................................... 194 figure 5-9 usb bl ock diagram ................................................................................................... . 216 figure 5-10 wakeup in terrupt oper ation flow............................................................................ 218 figure 5-11 endpoint sram structure ........................................................................................ 219 figure 5-12 setup transaction follo wed by data in transaction ................................................. 220 figure 5-13 data out transfer .................................................................................................. ... 220 figure 5-14 push -pull output................................................................................................... .... 241 figure 5-15 open -drain output .................................................................................................. . 242 figure 5-16 quasi-bidi rectional i/o mode .................................................................................... 242 figure 5-17 i 2 c bus timing .......................................................................................................... 259 figure 5-18 i 2 c protocol............................................................................................................... 261 figure 5-19 master tran smits data to slave ............................................................................... 261 figure 5-20 master read s data from slave ................................................................................ 261 figure 5-21 start an d stop condition..................................................................................... 262 figure 5-22 bit transfer on the i 2 c bus ....................................................................................... 263 figure 5-23 acknowledge on the i 2 c bus..................................................................................... 263 figure 5-24 i 2 c data shifti ng direction ........................................................................................ 265 figure 5-25: i 2 c time-out count block diagram ......................................................................... 266 figure 5-26 legend for th e following fi ve figures ......................................................................... 277 figure 5-27 master transmitte r mode ......................................................................................... 278 figure 5-28 master receiver mode.............................................................................................. 279 figure 5-29 slave transmitte r mode............................................................................................ 280 figure 5-30 slave receiver mode................................................................................................ 281 figure 5-31 gc mode ............................................................................................................ ...... 282 figure 5-32 pwm generator 0 clock source control.................................................................. 285 figure 5-33 pwm generator 0 architecture diagram.................................................................. 285 figure 5-34 pwm generator 2 clock source control.................................................................. 286 figure 5-35 pwm generator 2 architecture diagram.................................................................. 286 figure 5-36 pwm generator 4 clock source control.................................................................. 287 figure 5-37 pwm generator 4 architecture diagram.................................................................. 287 figure 5-38 pwm generator 6 clock source control.................................................................. 288 figure 5-39 pwm generator 6 architecture diagram.................................................................. 288 figure 5-40 legend of internal co mparator output of pwm-timer ............................................ 289 figure 5-41 pwm-time r operatio n timing.................................................................................. 290 figure 5-42 pwm double buffering illu stration............................................................................ 290 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 9 - revision v1.06 figure 5-43 pwm controller output du ty ratio ........................................................................... 291 figure 5-44 paired-pwm output wi th dead zone genera tion operation ................................... 291 figure 5-45 capture operation timing ........................................................................................ 292 figure 5-46 pwm group a pwm-timer in terrupt architec ture diagram..................................... 293 figure 5-47 pwm group b pwm-timer in terrupt architec ture diagram..................................... 293 figure 5-48 rtc block diagram .................................................................................................. 323 figure 5-49 spi block diagram.................................................................................................. .. 342 figure 5-50 spi master mode application bl ock diagram........................................................... 343 figure 5-51 spi slave mode a pplication blo ck diag ram............................................................. 343 figure 5-52 variable seri al clock frequency .............................................................................. 345 figure 5-53 32-bit in one tran saction.......................................................................................... 345 figure 5-54 two transactions in one transfer (b urst mode) ..................................................... 346 figure 5-55 byte reor der............................................................................................................. 347 figure 5-56 timing waveform for byte suspend......................................................................... 348 figure 5-57 two bits transfer mode............................................................................................ 349 figure 5-58 spi timi ng in mast er mode ...................................................................................... 350 figure 5-59 spi timing in master mode (alternate ph ase of spiclk) ....................................... 351 figure 5-60 spi timi ng in slav e mode ........................................................................................ 351 figure 5-61 spi timing in slave mode (alternate ph ase of spiclk) ......................................... 352 figure 5-62 timer contro ller block diagram ............................................................................... 367 figure 5-63 clock source of timer controller ............................................................................. 367 figure 5-64 timing of in terrupt and re set signal ........................................................................ 376 figure 5-65 watchdog ti mer clock control................................................................................. 377 figure 5-66 watchdog timer bloc k diagram............................................................................... 377 figure 5-67 uart cloc k control diagram................................................................................... 384 figure 5-68 uart block diagram................................................................................................ 384 figure 5-69 auto flow control bloc k diagram............................................................................. 386 figure 5-70 irda block diagram ................................................................................................. . 387 figure 5-71 irda tx /rx timing diagram .................................................................................... 388 figure 5-72 structur e of lin frame ............................................................................................. 389 figure 5-73 structur e of rs- 485 frame ...................................................................................... 391 figure 5-74 can bu s block diagram........................................................................................... 420 figure 5-75 format of data frame .......................................................................................... 422 figure 5-76 standard format in arbitrat ion field .............................................................. 423 figure 5-77 extended format in arbitrat ion field.............................................................. 423 figure 5-78 format of control field .................................................................................... 424 figure 5-79 format of crc field .............................................................................................. 425 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 10 - revision v1.06 figure 5-80 format of ack field............................................................................................... 426 figure 5-81 format of remote frame .................................................................................... 427 figure 5-82 format of error frame....................................................................................... 427 figure 5-83 ps/2 devi ce block diagram ..................................................................................... 454 figure 5-84 data format of device-to-host................................................................................. 456 figure 5-85 data format of host-to-device................................................................................. 456 figure 5-86 ps/2 bit data format............................................................................................... . 457 figure 5-87 ps/ 2 bus timing .................................................................................................... ... 457 figure 5-88 ps/2 data format ................................................................................................... .. 459 figure 5-89 i 2 s clock contro l diagram........................................................................................ 469 figure 5-90 i 2 s controller bl ock diagram .................................................................................... 469 figure 5-91 i 2 s bus timing diagr am (format =0) ....................................................................... 470 figure 5-92 msb justified timing diagram (format=1) .............................................................. 470 figure 5-93 fifo contents for various i 2 s modes ....................................................................... 471 figure 5-94 adc contro ller block diagram ................................................................................. 486 figure 5-95 adc converter se lf-calibration timing diagram ..................................................... 487 figure 5-96 adc clock control.................................................................................................. .. 488 figure 5-97 single mode c onversion timi ng diagram ................................................................ 488 figure 5-98 single-cycle scan on enabled channels timing di agram ...................................... 489 figure 5-99 continuous scan on e nabled channels ti ming diagram ........................................ 490 figure 5-100 a/d conversion re sult monitor logics diagram .................................................... 491 figure 5-101 a/d c ontroller in terrupt.......................................................................................... . 492 figure 5-102 adc single-end input conversion vo ltage and conversion result mapping diagram ..................................................................................................................................................... 496 figure 5-103 adc differential input conversion voltage and conversion result mapping diagram ..................................................................................................................................................... 496 figure 5-104 analog compar ator block diagram ........................................................................ 509 figure 5-105 compar ator controller in terrupt sources ............................................................... 510 figure 5-106 medium density pd ma controller bl ock diagram ................................................. 516 figure 5-107 low density pdma controller bl ock diagram........................................................ 517 figure 5-108 ebi block diagram................................................................................................ . 542 figure 5-109 connection of 16-bit ebi data width wi th 16-bit device ....................................... 543 figure 5-110 connection of 8-bit ebi data width with 8-bit device ............................................ 543 figure 5-111 timing control wa veform for 16bit data width..................................................... 545 figure 5-112 timing control wa veform for 8bit data width....................................................... 546 figure 5-113 timing control wavefo rm for insert idle cycle....................................................... 547 figure 6-1 medium density flash memory control block diagram............................................. 552 figure 6-2 low density flash memory control bl ock diagram ................................................... 553 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 11 - revision v1.06 figure 6-3 low density fl ash mem ory organization................................................................... 555 figure 6-4 low density fl ash memory organization................................................................... 556 figure 6-5 medium density flash memory structure .................................................................. 557 figure 6-6 low density fl ash memory structure......................................................................... 558 figure 7-1 typical crysta l applicatio n circuit .............................................................................. 589 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 12 - revision v1.06 tables table 1-1 connectivit y supported table........................................................................................ 13 table 5-1 address space assign ments for on-chi p contro llers................................................. 117 table 5-2 exc eption model ...................................................................................................... .... 160 table 5-3 system interrupt map................................................................................................. .. 161 table 5-4 vector table format .................................................................................................. .. 162 table 5-5 power down mode contro l table................................................................................ 198 table 5-6 byte order and byte suspend conditions ................................................................... 348 table 5-7 watchdog timeout interval selection .......................................................................... 375 table 5-8 uart b aud rate e quation .......................................................................................... 381 table 5-9 uart baud rate setti ng table................................................................................... 382 table 5-10 uart interrupt sources and flags table in dma mode (low density only)........... 411 table 5-11 uart interrupt sources and flags table in software mode .................................... 411 table 5-12 baud rate equation table............................................................................................ 414 table 6-1 medium densit y memory address map....................................................................... 554 table 6-2 low density memory address map ............................................................................. 554 table 6-3 isp mode ............................................................................................................. ........ 564 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 13 - revision v1.06 1 general description the numicro ? nuc100 series is 32-bit microcontrollers with embedded arm ? cortex?-m0 core for industrial control and applications which need rich communication interfaces. the cortex?-m0 is the newest arm ? embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. numicro ? nuc100 series includes nuc100, nuc120, nuc130 and nuc140 product line. the numicro ? nuc100 advanced line embeds cortex?- m0 core running up to 50 mhz with 32k/64k/128k-byte embedded flash, 4k/8k/16k -byte embedded sram, and 4k-byte loader rom for the isp. it also equips with plenty of peripheral devices, such as timers, watchdog timer, rtc, pdma, uart, spi/microwire, i 2 c, i 2 s, pwm timer, gpio, ps2, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. the numicro ? nuc120 usb line with usb 2.0 full-speed function embeds cortex?-m0 core running up to 50 mhz with 32k/64k/128k-byt e embedded flash, 4k/8k/16k-byte embedded sram, and 4k-byte loader rom for the isp. it also equips with plenty of peripheral devices, such as timers, watchdog timer, rtc, pdma, uart, spi/microwire, i 2 c, i 2 s, pwm timer, gpio, ps2, usb 2.0 fs device, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. the numicro ? nuc130 automotive line with can function embeds cortex?-m0 core running up to 50 mhz with 64k/128k-byte embedded flas h, 8k/16k-byte embedded sram, and 4k-byte loader rom for the isp.. it also equips with pl enty of peripheral devices, such as timers, watchdog timer, rtc, pdma , uart, spi/microwire, i 2 c, i 2 s, pwm timer, gpio, lin, can, ps2, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. the numicro ? nuc140 connectivity line with usb 2. 0 full-speed and can functions embeds cortex?-m0 core running up to 50 mhz with 64k/128k-byte embedded flash, 8k/16k-byte embedded sram, and 4k-byte loader rom for the isp.. it also equips with plenty of peripheral devices, such as timers, watchdog time r, rtc, pdma, uart, spi/microwire, i 2 c, i 2 s, pwm timer, gpio, lin, can, ps2, usb 2.0 fs devi ce, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. product line uart spi i 2 c usb lin can ps2 i 2 s nuc100 nuc120 nuc130 nuc140 table 1-1 connectivity supported table numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 14 - revision v1.06 2 features the equipped features are dependent on the product line and their sub products. 2.1 numicro ? nuc100 features ? advanced line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep-mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5v to 5.5v ? flash eprom memory C 32k/64k/128k bytes flash eprom for program code (128kb only support in medium density) C 4kb flash for isp loader C support in-system program(i sp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for the 32kb and 64kb system (only support 4kb data flash in low density) C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k/16k bytes embedded sram (16kb only support in medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in low density) ? clock control C flexible selection for different applications C build-in 22.1184 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wakeup sleep operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz crystal input for precise timing operation C external 32.768 khz crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 15 - revision v1.06 ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle an d auto-reload counting operation modes ? watch dog timer C multiple clock sources C 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) C wdt can wake up from power down or sleep mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (low density only support 2 uart controllers) C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) function C support rs-485 9 bit mode and direct ion control. (low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller C master up to 20 mhz, and slave up to 10 mhz C support spi/microwire master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C suppo rt byte suspend mode in 32-bit transmission C support pdma mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 16 - revision v1.06 ? i 2 c C up to two sets of i2c device C master/slave up to 1mbit/s C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8, 16, 24 and 32 bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? ps2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? ebi (external bus interface) support (low density 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8bit/16bit data width C support byte write in 16bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode ? analog comparator C up to two analog comparator C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5v/3.8v/2.7v/2.2v numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 17 - revision v1.06 C support brownout interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for medium density only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 18 - revision v1.06 2.2 numicro ? nuc120 features ? usb line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep-mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5v to 5.5v ? flash eprom memory C 32k/64k/128k bytes flash eprom for program code (128kb only support in medium density) C 4kb flash for isp loader C support in-system program(i sp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for the 32kb and 64kb system (only support 4kb data flash in low density) C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k/16k bytes embedded sram (16kb only support in medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in low density) ? clock control C flexible selection for different applications C build-in 22.1184 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wakeup sleep operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz crystal input for usb and precise timing operation C external 32.768 khz crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle an d auto-reload counting operation modes numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 19 - revision v1.06 ? watch dog timer C multiple clock sources C 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) C wdt can wake up from power down or sleep mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (low density only support 2 uart controllers) C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) function C support rs-485 9 bit mode and direct ion control. (low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller C master up to 20 mhz, and slave up to 10 mhz C support spi/microwire master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 20 - revision v1.06 ? i 2 c C up to two sets of i 2 c device C master/slave up to 1mbit/s C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8, 16, 24 and 32 bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? ps2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? usb 2.0 full-speed device C one set of usb 2.0 fs device 12mbps C on-chip usb transceiver C provide 1 interrupt source with 4 interrupt events C support control, bulk in/out, in terrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide 6 programmable endpoints C include 512 bytes internal sram as usb buffer C provide remote wakeup capability ? ebi (external bus interface) support (low density 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8bit/16bit data width C support byte write in 16bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 21 - revision v1.06 ? analog comparator C up to two analog comparator C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5v/3.8v/2.7v/2.2v C support brownout interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for medium density only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 22 - revision v1.06 2.3 numicro ? nuc130 features ? automotive line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep-mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5v to 5.5v ? flash eprom memory C 64k/128k bytes flash eprom for program code (128kb only support in medium density) C 4kb flash for isp loader C support in-system program (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for 64kb system (only support 4kb data flash in low density) C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 8k/16k bytes embedded sram (16kb only support in medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in low density) ? clock control C flexible selection for different applications C build-in 22.1184 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wakeup sleep operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz crystal input for precise timing operation C external 32.768 khz crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle an d auto-reload counting operation modes numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 23 - revision v1.06 ? watch dog timer C multiple clock sources C 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) C wdt can wake up from power down or sleep mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (low density only support 2 uart controllers) C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) and lin function C support rs-485 9 bit mode and direct ion control. (low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller C master up to 20 mhz, and slave up to 10 mhz C support spi/microwire master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 24 - revision v1.06 ? i 2 c C up to two sets of i 2 c device C master/slave up to 1mbit/s C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8, 16, 24 and 32 bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? ps2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? can 2.0 C can 2.0b protocol compatible device C support 11-bit identifier as well as 29-bit identifier C bit rates up to 1mbits/s C nrz bit coding/ encoding C error detection & status report ? bit error, form error, stuffing error, 15-bit crc detection, and acknowledge error interrupt ? each can-bus error and transmission/receive done C bit timing synchronization C acceptance filter extension C sleep mode wake up ? ebi (external bus interface) support (low density 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8bit/16bit data width C support byte write in 16bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 25 - revision v1.06 C threshold voltage detection C conversion start by software programming or external input C support pdma mode ? analog comparator C up to two analog comparator C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5v/3.8v/2.7v/2.2v C support brownout interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for medium density only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 26 - revision v1.06 2.4 numicro ? nuc140 features ? connectivity line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep-mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5v to 5.5v ? flash eprom memory C 64k/128k bytes flash eprom for program code (128kb only support in medium density) C 4kb flash for isp loader C support in-system program (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for 64kb system (only support 4kb data flash in low density) C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 8k/16k bytes embedded sram (16kb only support in medium density) C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals (only support 1 channel in low density) ? clock control C flexible selection for different applications C build-in 22.1184 mhz osc (trimmed to 1%) for system operation, and low power 10 khz osc for watchdog and wakeup sleep operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz crystal input for usb and precise timing operation C external 32.768 khz crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle an d auto-reload counting operation modes numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 27 - revision v1.06 ? watch dog timer C multiple clock sources C 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) C wdt can wake up from power down or sleep mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers (low density only support 2 uart controllers). C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 63-byte fifo is for high speed C uart1/2(optional) with 15-byte fifo for standard device C support irda (sir) and lin function C support rs-485 9 bit mode and direct ion control. (low density only) C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller C master up to 20 mhz, and slave up to 10 mhz C support spi/microwire master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 28 - revision v1.06 ? i 2 c C up to two sets of i 2 c device C master/slave up to 1mbit/s C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8, 16, 24 and 32 bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? can 2.0 C can 2.0b protocol compatible device C support 11-bit identifier as well as 29-bit identifier C bit rates up to 1mbits/s C nrz bit coding/ encoding C error detection & status report ? bit error, form error, stuffing error, 15-bit crc detection, and acknowledge error interrupt ? each can-bus error and transmission/receive done C bit timing synchronization C acceptance filter extension C sleep mode wake up ? ps2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? usb 2.0 full-speed device C one set of usb 2.0 fs device 12mbps C on-chip usb transceiver C provide 1 interrupt source with 4 interrupt events C support control, bulk in/out, in terrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide 6 programmable endpoints C include 512 bytes internal sram as usb buffer C provide remote wakeup capability ? ebi (external bus interface) support (low density 64-pin package only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 29 - revision v1.06 C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8bit/16bit data width C support byte write in 16bit data width mode ? adc C 12-bit sar adc with 600k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode ? analog comparator C up to two analog comparator C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5v/3.8v/2.7v/2.2v C support brownout interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin (100-pin for medium density only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 30 - revision v1.06 3 parts information list and pin configuration 3.1 numicro ? nuc100 products selection guide 3.1.1 numicro ? nuc100 medium density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100ld3an 64 kb 16 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100le3an 128 kb 16 kb definable 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 6 8x12-bit v - v lqfp48 nuc100rd3an 64 kb 16 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 nuc100re3an 128 kb 16 kb definable 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 6 8x12-bit v - v lqfp64 nuc100vd2an 64 kb 8 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100vd3an 64 kb 16 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 nuc100ve3an 128 kb 16 kb definable 4 kb up to 80 4x32-bit 3 4 2 - - - 1 2 8 8x12-bit v - v lqfp100 3.1.2 numicro ? nuc100 low density advance line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc100lc1bn 32 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld1bn 64 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100ld2bn 64 kb 8 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - - - 1 1 4 8x12-bit v - v lqfp48 nuc100rc1bn 32 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd1bn 64 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 nuc100rd2bn 64 kb 8 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - - - 1 2 4 8x12-bit v v v lqfp64 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 31 - revision v1.06 3.2 numicro ? nuc120 products selection guide 3.2.1 numicro ? nuc120 medium density usb line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc120ld3an 64 kb 16 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 - - 1 1 4 8x12-bit v - v lqfp48 nuc120le3an 128 kb 16 kb definable 4 kb up to 31 4x32-bit 2 1 2 1 - - 1 1 4 8x12-bit v - v lqfp48 nuc120rd3an 64 kb 16 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 - - 1 2 6 8x12-bit v - v lqfp64 nuc120re3an 128 kb 16 kb definable 4 kb up to 45 4x32-bit 2 2 2 1 - - 1 2 6 8x12-bit v - v lqfp64 nuc120vd2an 64 kb 8 kb 4 kb 4 kb up to 76 4x32-bit 3 4 2 1 - - 1 2 8 8x12-bit v - v lqfp100 nuc120vd3an 64 kb 16 kb 4 kb 4 kb up to 76 4x32-bit 3 4 2 1 - - 1 2 8 8x12-bit v - v lqfp100 NUC120VE3AN 128 kb 16 kb definable 4 kb up to 76 4x32-bit 3 4 2 1 - - 1 2 8 8x12-bit v - v lqfp100 3.2.2 numicro ? nuc120 low density usb line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc120lc1bn 32 kb 4 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 - - 1 1 4 8x12-bit v - v lqfp48 nuc120ld1bn 64 kb 4 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 - - 1 1 4 8x12-bit v - v lqfp48 nuc120ld2bn 64 kb 8 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 - - 1 1 4 8x12-bit v - v lqfp48 nuc120rc1bn 32 kb 4 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 - - 1 2 4 8x12-bit v v v lqfp64 nuc120rd1bn 64 kb 4 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 - - 1 2 4 8x12-bit v v v lqfp64 nuc120rd2bn 64 kb 8 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 - - 1 2 4 8x12-bit v v v lqfp64 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 32 - revision v1.06 3.3 numicro ? nuc130 products selection guide 3.3.1 numicro ? nuc130 medium density auto motive line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc130ld3an 64 kb 16 kb 4 kb 4 kb up to 35 4x32-bit 3 1 2 - 2 1 1 1 4 8x12-bit v - v lqfp48 nuc130le3an 128 kb 16 kb definable 4 kb up to 35 4x32-bit 3 1 2 - 2 1 1 1 4 8x12-bit v - v lqfp48 nuc130rd3an 64 kb 16 kb 4 kb 4 kb up to 49 4x32-bit 3 2 2 - 2 1 1 2 6 8x12-bit v - v lqfp64 nuc130re3an 128 kb 16 kb definable 4 kb up to 49 4x32-bit 3 2 2 - 2 1 1 2 6 8x12-bit v - v lqfp64 nuc130vd2an 64 kb 8 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - 2 1 1 2 8 8x12-bit v - v lqfp100 nuc130vd3an 64 kb 16 kb 4 kb 4 kb up to 80 4x32-bit 3 4 2 - 2 1 1 2 8 8x12-bit v - v lqfp100 nuc130ve3an 128 kb 16 kb definable 4 kb up to 80 4x32-bit 3 4 2 - 2 1 1 2 8 8x12-bit v - v lqfp100 3.3.2 numicro ? nuc130 low density automotive line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc130lc1bn 32 kb 4 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - 2 1 1 1 4 8x12-bit v - v lqfp48 nuc130ld2bn 64 kb 8 kb 4 kb 4 kb up to 35 4x32-bit 2 1 2 - 2 1 1 1 4 8x12-bit v - v lqfp48 nuc130rc1bn 32 kb 4 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - 2 1 1 2 4 8x12-bit v v v lqfp64 nuc130rd2bn 64 kb 8 kb 4 kb 4 kb up to 49 4x32-bit 2 2 2 - 2 1 1 2 4 8x12-bit v v v lqfp64 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 33 - revision v1.06 3.4 numicro ? nuc140 products selection guide 3.4.1 numicro ? nuc140 medium density connectivity line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc140ld3an 64 kb 16 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140le3an 128 kb 16 kb definable 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140rd3an 64 kb 16 kb 4 kb 4 kb up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v - v lqfp64 nuc140re3an 128 kb 16 kb definable 4 kb up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v - v lqfp64 nuc140vd2an 64 kb 8 kb 4 kb 4 kb up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v - v lqfp100 nuc140vd3an 64 kb 16 kb 4 kb 4 kb up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v - v lqfp100 nuc140ve3an 128 kb 16 kb definable 4 kb up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v - v lqfp100 3.4.2 numicro ? nuc140 low density connectivity line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc140lc1bn 32 kb 4 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140ld2bn 64 kb 8 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140rc1bn 32 kb 4 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 2 1 1 2 4 8x12-bit v v v lqfp64 nuc140rd2bn 64 kb 8 kb 4 kb 4 kb up to 45 4x32-bit 2 2 2 1 2 1 1 2 4 8x12-bit v v v lqfp64 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 34 - revision v1.06 nuc 1 0 -xx arm-based 32-bit microcontroller 0: advance line 2: usb line 3: automotive line 4: connectivity line cpu core 1: cortex-m0 5/7: arm7 9: arm9 temperature n: -40 ~ +85 e: -40 ~ +105 c: -40 ~ +125 reserve x x function 0 package type y: qfn 36 l: lqfp 48 r: lqfp 64 v: lqfp 100 x ram size 1: 4k 2: 8k 3: 16k aprom size a: 8k b: 16k c: 32k d: 64k e: 128k figure 3-1 numicro ? nuc100 series selection code numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 35 - revision v1.06 3.5 pin configuration 3.5.1 numicro ? nuc100/nuc120/nuc130/nuc140 medium density pin diagram 3.5.1.1 numicro ? nuc100 lqfp 100 pin adc5/pa.5 adc6/pa.6 adc7/spiss21/pa.7 spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/tx2 pd.14/rx2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/tx0 pb.0/rx0 d+ d- vdd33 vbus 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 nuc100 medium density lqfp 100-pin 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 42 43 44 45 46 47 48 49 50 pe.7 pe.8 pc.4/miso01 pc.5/mosi01 pb.9/spiss11/tm1 pb.10/spiss01/tm2 pb.11/tm3/pwm4 pe.5/pwm5 pe.6 51 52 53 54 55 56 57 58 59 vss vdd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 84 83 82 81 80 79 78 77 76 ps2dat ps2clk spiss20/pd.0 spiclk2/pd.1 miso20/pd.2 mosi20/pd.3 miso21/pd.4 mosi21/pd.5 vref figure 3-2 numicro ? nuc100 medium density lqfp 100-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 36 - revision v1.06 3.5.1.2 numicro ? nuc100 lqfp 64 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9/tm1 pb.10/tm2 pb.11/tm3/pwm4 pe.5/pwm5 pd.15/tx2 pd.14/rx2 pd.7 pd.6 pb.3/cts0 pb.2/rts0 pb.1/tx0 pb.0/rx0 nuc100 medium density lqfp 64-pin figure 3-3 numicro ? nuc100 medium density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 37 - revision v1.06 3.5.1.3 numicro ? nuc100 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-4 numicro ? nuc100 medium density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 38 - revision v1.06 3.5.1.4 numicro ? nuc120 lqfp 100 pin spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 51 52 53 54 55 56 57 58 59 vss vdd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 figure 3-5 numicro ? nuc120 medium density lqfp 100-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 39 - revision v1.06 3.5.1.5 numicro ? nuc120 lqfp 64 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo d+ d- vdd33 vbus 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9/tm1 pb.10/tm2 pb.11/tm3/pwm4 pe.5/pwm5 pb.3/cts0 pb.2/rts0 pb.1/tx0 pb.0/rx0 nuc120 medium density lqfp 64-pin figure 3-6 numicro ? nuc120 medium density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 40 - revision v1.06 3.5.1.6 numicro ? nuc120 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-7 numicro ? nuc120 medium density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 41 - revision v1.06 3.5.1.7 numicro ? nuc130 lqfp 100 pin spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 51 52 53 54 55 56 57 58 59 vss vdd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 figure 3-8 numicro ? nuc130 medium density lqfp 100-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 42 - revision v1.06 3.5.1.8 numicro ? nuc130 lqfp 64 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss cpn0/pc.7 cpp0/pc.6 cpn1/pc.15 cpp1/pc.14 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 avdd vss vdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/tx2 pd.14/rx2 pd.7/cantx0 pd.6/canrx0 pb.3/cts0 pb.2/rts0 pb.1/tx0 pb.0/rx0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 pb.9/tm1 pb.10/tm2 pb.11/tm3/pwm4 pe.5/pwm5 nuc130 medium density lqfp 64-pin figure 3-9 numicro ? nuc130 medium density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 43 - revision v1.06 3.5.1.9 numicro ? nuc130 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-10 numicro ? nuc130 medium density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 44 - revision v1.06 3.5.1.10 numicro ? nuc140 lqfp 100 pin spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 51 52 53 54 55 56 57 58 59 vss vdd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 figure 3-11 numicro ? nuc140 medium density lqfp 100-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 45 - revision v1.06 3.5.1.11 numicro ? nuc140 lqfp 64 pin spiss31/int0/pb.14 cpo1/pb.13 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 rts1/pb.6 cts1/pb.7 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 figure 3-12 numicro ? nuc140 medium density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 46 - revision v1.06 3.5.1.12 numicro ? nuc140 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-13 numicro ? nuc140 medium density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 47 - revision v1.06 3.5.2 numicro ? nuc100/120/130/140 low density pin diagram 3.5.2.1 numicro ? nuc100 lqfp 64 pin figure 3-14 numicro ? nuc100 low density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 48 - revision v1.06 3.5.2.2 numicro ? nuc100 lqfp 48 pin figure 3-15 numicro ? nuc100 low density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 49 - revision v1.06 3.5.2.3 numicro ? nuc120 lqfp 64 pin figure 3-16 numicro ? nuc120 low density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 50 - revision v1.06 3.5.2.4 numicro ? nuc120 lqfp 48 pin adc5/pa.5 adc6/pa.6 adc7/pa.7 clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss cpn0/pc.7 cpp0/pc.6 int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk avdd pvss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pb.3/cts0 pb.2/rts0 pb.1/tx0 pb.0/rx0 d+ d- vdd33 vbus 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 nuc120 low density lqfp 48-pin figure 3-17 numicro ? nuc120 low density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 51 - revision v1.06 3.5.2.5 numicro ? nuc130 lqfp 64 pin figure 3-18 numicro ? nuc130 low density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 52 - revision v1.06 3.5.2.6 numicro ? nuc130 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-19 numicro ? nuc130 low density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 53 - revision v1.06 3.5.2.7 numicro ? nuc140 lqfp 64 pin figure 3-20 numicro ? nuc140 low density lqfp 64-pin pin diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 54 - revision v1.06 3.5.2.8 numicro ? nuc140 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rx1/pb.4 tx1/pb.5 ldo vdd vss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 avss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-21 numicro ? nuc140 low density lqfp 48-pin pin diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 55 - revision v1.06 3.6 pin description 3.6.1 numicro ? nuc100/nuc120/nuc130/nuc140 medium density pin description 3.6.1.1 numicro ? nuc100 medium density pin description pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 1 pe.15 i/o general purpose input/output digital pin 2 pe.14 i/o general purpose input/output digital pin 3 pe.13 i/o general purpose input/output digital pin pb.14 i/o general purpose input/output digital pin /int0 i /int0: external interrupt1 input pin 4 1 spiss31 i/o spiss31: spi3 2 nd slave select pin pb.13 i/o general purpose input/output digital pin 5 2 cpo1 o comparator1 output pin pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 6 3 1 clko o frequency divider output pin 7 4 2 x32o o external 32.768 kh z crystal output pin 8 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 9 6 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 10 7 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin pa.9 i/o general purpose input/output digital pin 11 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 12 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pd.8 i/o general purpose input/output digital pin 13 spiss30 i/o spiss30: spi3 slave select pin pd.9 i/o general purpose input/output digital pin 14 spiclk3 i/o spiclk3: spi3 serial clock pin 15 pd.10 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 56 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description miso30 i miso30: spi3 miso (master in, slave out) pin pd.11 i/o general purpose input/output digital pin 16 mosi30 o mosi30: spi3 mosi (master out, slave in) pin pd.12 i/o general purpose input/output digital pin 17 miso31 i miso31: spi3 2 nd miso (master in, slave out) pin pd.13 i/o general purpose input/output digital pin 18 mosi31 o mosi31: spi3 2 nd mosi (master out, slave in) pin pb.4 i/o general purpose input/output digital pin 19 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 20 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 21 12 rts1 rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 22 13 cts1 cts1: clear to send input pin for uart1 23 14 10 ldo p ldo output pin 24 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 25 16 12 vss p ground 26 pe.12 i/o general purpose input/output digital pin 27 pe.11 i/o general purpose input/output digital pin 28 pe.10 i/o general purpose input/output digital pin 29 pe.9 i/o general purpose input/output digital pin 30 pe.8 i/o general purpose input/output digital pin 31 pe.7 i/o general purpose input/output digital pin pb.0 i/o general purpose input/output digital pin 32 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 33 18 14 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 34 19 15 rts0 rts0: request to send output pin for uart0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 57 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pb.3 i/o general purpose input/output digital pin 35 20 16 cts0 cts0: clear to send input pin for uart0 36 21 pd.6 i/o general purpose input/output digital pin 37 22 pd.7 i/o general purpose input/output digital pin pd.14 i/o general purpose input/output digital pin 38 23 rxd2 i rxd2: data receiver input pin for uart2 pd.15 i/o general purpose input/output digital pin 39 24 txd2 o txd2: data transmitter output pin for uart2 pc.5 i/o general purpose input/output digital pin 40 mosi01 o mosi01: spi0 2 nd mosi (master out, slave in) pin pc.4 i/o general purpose input/output digital pin 41 miso01 i miso01: spi0 2 nd miso (master in, slave out) pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 42 25 17 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 43 26 18 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 44 27 19 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 45 28 20 i2slrcl k i/o i2slrclk: i 2 s left right channel clock 46 pe.6 i/o general purpose input/output digital pin pe.5 i/o general purpose input/output digital pin 47 29 21 pwm5 o pwm5: pwm output pb.11 i/o general purpose input/output digital pin tm3 o tm3: timer3 external counter input 48 30 22 pwm4 o pwm4: pwm output numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 58 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pb.10 i/o general purpose input/output digital pin 31 23 tm2 o tm2: timer2 external counter input 49 spiss01 i/o spiss01: spi0 2 nd slave select pin pb.9 i/o general purpose input/output digital pin 32 24 tm1 o tm1: timer1 external counter input 50 spiss11 i/o spiss11: spi1 2 nd slave select pin 51 pe.4 i/o general purpose input/output digital pin 52 pe.3 i/o general purpose input/output digital pin 53 pe.2 i/o general purpose input/output digital pin pe.1 i/o general purpose input/output digital pin 54 pwm7 o pwm7: pwm output pe.0 i/o general purpose input/output digital pin 55 pwm6 o pwm6: pwm output pc.13 i/o general purpose input/output digital pin 56 mosi11 o mosi11: spi1 2 nd mosi (master out, slave in) pin pc.12 i/o general purpose input/output digital pin 57 miso11 i miso11: spi1 2 nd miso (master in, slave out) pin pc.11 i/o general purpose input/output digital pin 58 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 59 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 60 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 61 36 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 62 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 63 38 26 pwm2 o pwm2: pwm output numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 59 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pa.13 i/o general purpose input/output digital pin 64 39 27 pwm1 o pwm1: pwm output pa.12 i/o general purpose input/output digital pin 65 40 28 pwm0 o pwm0: pwm output 66 41 29 ice_dat i/o serial wired debugger data pin 67 42 30 ice_ck i serial wired debugger clock pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 vss p ground 70 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 71 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 72 45 33 adc1 ai adc1: adc analog input pa.2 i/o general purpose input/output digital pin 73 46 34 adc2 ai adc2: adc analog input pa.3 i/o general purpose input/output digital pin 74 47 35 adc3 ai adc3: adc analog input pa.4 i/o general purpose input/output digital pin 75 48 36 adc4 ai adc4: adc analog input pa.5 i/o general purpose input/output digital pin 76 49 37 adc5 ai adc5: adc analog input pa.6 i/o general purpose input/output digital pin 77 50 38 adc6 ai adc6: adc analog input pa.7 i/o general purpose input/output digital pin 51 39 adc7 ai adc7: adc analog input 78 spiss21 i/o spiss21: spi2 2 nd slave select pin 79 vref ap voltage reference input for adc 80 52 40 avdd ap power supply for internal analog circuit pd.0 i/o general purpose input/output digital pin 81 spiss20 i/o spiss20: spi2 slave select pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 60 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pd.1 i/o general purpose input/output digital pin 82 spiclk2 i/o spiclk2: spi2 serial clock pin pd.2 i/o general purpose input/output digital pin 83 miso20 i miso20: spi2 miso (master in, slave out) pin pd.3 i/o general purpose input/output digital pin 84 mosi20 o mosi20: spi2 mosi (master out, slave in) pin pd.4 i/o general purpose input/output digital pin 85 miso21 i miso21: spi2 2 nd miso (master in, slave out) pin pd.5 i/o general purpose input/output digital pin 86 mosi21 o mosi21: spi2 2 nd mosi (master out, slave in) pin pc.7 i/o general purpose input/output digital pin 87 53 41 cpn0 i cpn0: comparator0 negative input pin pc.6 i/o general purpose input/output digital pin 88 54 42 cpp0 i cpp0: comparator0 positive input pin pc.15 i/o general purpose input/output digital pin 89 55 cpn1 i cpn1: comparator1 negative input pin pc.14 i/o general purpose input/output digital pin 90 56 cpp1 i cpp1: comparator1 positive input pin pb.15 i/o general purpose input/output digital pin 91 57 43 /int1 i /int1: external interrupt0 input pin 92 58 44 xt1_out o external 4~24 mhz crystal output pin 93 59 45 xt1_in i external 4~24 mhz crystal input pin 94 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 ps2dat i/o ps2 data pin 98 ps2clk i/o ps2 clock pin 99 63 47 pvss p pll ground 100 64 48 pb.8 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 61 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description stadc i stadc: adc external trigger input. tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 62 - revision v1.06 3.6.1.2 numicro ? nuc120 medium density pin description pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 1 pe.15 i/o general purpose input/output digital pin 2 pe.14 i/o general purpose input/output digital pin 3 pe.13 i/o general purpose input/output digital pin pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin 4 spiss31 i/o spiss31: spi3 2 nd slave select pin pb.13 i/o general purpose input/output digital pin 5 2 cpo1 o comparator1 output pin pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 6 3 1 clko o frequency divider output pin 7 4 2 x32o o external 32.768 kh z crystal output pin 8 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 9 6 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 10 7 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin pa.9 i/o general purpose input/output digital pin 11 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 12 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pd.8 i/o general purpose input/output digital pin 13 spiss30 i/o spiss30: spi3 slave select pin pd.9 i/o general purpose input/output digital pin 14 spiclk3 i/o spiclk3: spi3 serial clock pin pd.10 i/o general purpose input/output digital pin 15 miso30 i miso30: spi3 miso (master in, slave out) pin 16 pd.11 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 63 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description mosi30 o mosi30: spi3 mosi (master out, slave in) pin pd.12 i/o general purpose input/output digital pin 17 miso31 i miso31: spi3 2 nd miso (master in, slave out) pin pd.13 i/o general purpose input/output digital pin 18 mosi31 o mosi31: spi3 2 nd mosi (master out, slave in) pin pb.4 i/o general purpose input/output digital pin 19 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 20 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 21 12 rts1 rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 22 13 cts1 cts1: clear to send input pin for uart1 23 14 10 ldo p ldo output pin 24 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 25 16 12 vss p ground 26 pe.8 i/o general purpose input/output digital pin 27 pe.7 i/o general purpose input/output digital pin 28 17 13 vbus usb power supply: from usb host or hub. 29 18 14 vdd33 usb internal power regulator output 3.3v decoupling pin 30 19 15 d- usb usb differential signal d- 31 20 16 d+ usb usb differential signal d+ pb.0 i/o general purpose input/output digital pin 32 21 17 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 33 22 18 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 34 23 19 rts0 rts0: request to send output pin for uart0 35 24 20 pb.3 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 64 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description cts0 cts0: clear to send input pin for uart0 36 pd.6 i/o general purpose input/output digital pin 37 pd.7 i/o general purpose input/output digital pin pd.14 i/o general purpose input/output digital pin 38 rxd2 i rxd2: data receiver input pin for uart2 pd.15 i/o general purpose input/output digital pin 39 txd2 o txd2: data transmitter output pin for uart2 pc.5 i/o general purpose input/output digital pin 40 mosi01 o mosi01: spi0 2 nd mosi (master out, slave in) pin pc.4 i/o general purpose input/output digital pin 41 miso01 i miso01: spi0 2 nd miso (master in, slave out) pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 42 25 21 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 43 26 22 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 44 27 23 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 45 28 24 i2slrcl k i/o i2slrclk: i 2 s left right channel clock 46 pe.6 i/o general purpose input/output digital pin pe.5 i/o general purpose input/output digital pin 47 29 pwm5 o pwm5: pwm output pb.11 i/o general purpose input/output digital pin tm3 o tm3: timer3 external counter input 48 30 pwm4 o pwm4: pwm output 49 31 pb.10 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 65 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description tm2 o tm2: timer2 external counter input spiss01 i/o spiss01: spi0 2 nd slave select pin pb.9 i/o general purpose input/output digital pin 32 tm1 o tm1: timer1 external counter input 50 spiss11 i/o spiss11: spi1 2 nd slave select pin 51 pe.4 i/o general purpose input/output digital pin 52 pe.3 i/o general purpose input/output digital pin 53 pe.2 i/o general purpose input/output digital pin pe.1 i/o general purpose input/output digital pin 54 pwm7 o pwm7: pwm output pe.0 i/o general purpose input/output digital pin 55 pwm6 o pwm6: pwm output pc.13 i/o general purpose input/output digital pin 56 mosi11 o mosi11: spi1 2 nd mosi (master out, slave in) pin pc.12 i/o general purpose input/output digital pin 57 miso11 i miso11: spi1 2 nd miso (master in, slave out) pin pc.11 i/o general purpose input/output digital pin 58 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 59 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 60 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 61 36 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 62 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 63 38 26 pwm2 o pwm2: pwm output 64 39 27 pa.13 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 66 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pwm1 o pwm1: pwm output pa.12 i/o general purpose input/output digital pin 65 40 28 pwm0 o pwm0: pwm output 66 41 29 ice_dat i/o serial wired debugger data pin 67 42 30 ice_ck i serial wired debugger clock pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 vss p ground 70 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 71 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 72 45 33 adc1 ai adc1: adc analog input pa.2 i/o general purpose input/output digital pin 73 46 34 adc2 ai adc2: adc analog input pa.3 i/o general purpose input/output digital pin 74 47 35 adc3 ai adc3: adc analog input pa.4 i/o general purpose input/output digital pin 75 48 36 adc4 ai adc4: adc analog input pa.5 i/o general purpose input/output digital pin 76 49 37 adc5 ai adc5: adc analog input pa.6 i/o general purpose input/output digital pin 77 50 38 adc6 ai adc6: adc analog input pa.7 i/o general purpose input/output digital pin 51 39 adc7 ai adc7: adc analog input 78 spiss21 i/o spiss21: spi2 2 nd slave select pin 79 vref ap voltage reference input for adc 80 52 40 avdd ap power supply for internal analog circuit pd.0 i/o general purpose input/output digital pin 81 spiss20 i/o spiss20: spi2 slave select pin 82 pd.1 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 67 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description spiclk2 i/o spiclk2: spi2 serial clock pin pd.2 i/o general purpose input/output digital pin 83 miso20 i miso20: spi2 miso (master in, slave out) pin pd.3 i/o general purpose input/output digital pin 84 mosi20 o mosi20: spi2 mosi (master out, slave in) pin pd.4 i/o general purpose input/output digital pin 85 miso21 i miso21: spi2 2 nd miso (master in, slave out) pin pd.5 i/o general purpose input/output digital pin 86 mosi21 o mosi21: spi2 2 nd mosi (master out, slave in) pin pc.7 i/o general purpose input/output digital pin 87 53 41 cpn0 i cpn0: comparator0 negative input pin pc.6 i/o general purpose input/output digital pin 88 54 42 cpp0 i cpp0: comparator0 positive input pin pc.15 i/o general purpose input/output digital pin 89 55 cpn1 i cpn1: comparator1 negative input pin pc.14 i/o general purpose input/output digital pin 90 56 cpp1 i cpp1: comparator1 positive input pin pb.15 i/o general purpose input/output digital pin 91 57 43 /int1 i /int1: external interrupt0 input pin 92 58 44 xt1_out o external 4~24 mhz crystal output pin 93 59 45 xt1_in i external 4~24 mhz crystal input pin 94 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 ps2dat i/o ps2 data pin 98 ps2clk i/o ps2 clock pin 99 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin 100 64 48 stadc i stadc: adc external trigger input. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 68 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 69 - revision v1.06 3.6.1.3 numicro ? nuc130 medium density pin description pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 1 pe.15 i/o general purpose input/output digital pin 2 pe.14 i/o general purpose input/output digital pin 3 pe.13 i/o general purpose input/output digital pin pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin 4 spiss31 i/o spiss31: spi3 2 nd slave select pin pb.13 i/o general purpose input/output digital pin 5 2 cpo1 o comparator1 output pin pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 6 3 1 clko o frequency divider output pin 7 4 2 x32o o external 32.768 kh z crystal output pin 8 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 9 6 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 10 7 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin pa.9 i/o general purpose input/output digital pin 11 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 12 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pd.8 i/o general purpose input/output digital pin 13 spiss30 i/o spiss30: spi3 slave select pin pd.9 i/o general purpose input/output digital pin 14 spiclk3 i/o spiclk3: spi3 serial clock pin pd.10 i/o general purpose input/output digital pin 15 miso30 i miso30: spi3 miso (master in, slave out) pin 16 pd.11 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 70 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description mosi30 o mosi30: spi3 mosi (master out, slave in) pin pd.12 i/o general purpose input/output digital pin 17 miso31 i miso31: spi3 2 nd miso (master in, slave out) pin pd.13 i/o general purpose input/output digital pin 18 mosi31 o mosi31: spi3 2 nd mosi (master out, slave in) pin pb.4 i/o general purpose input/output digital pin 19 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 20 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 21 12 rts1 rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 22 13 cts1 cts1: clear to send input pin for uart1 23 14 10 ldo p ldo output pin 24 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 25 16 12 vss p ground 26 pe.12 i/o general purpose input/output digital pin 27 pe.11 i/o general purpose input/output digital pin 28 pe.10 i/o general purpose input/output digital pin 29 pe.9 i/o general purpose input/output digital pin 30 pe.8 i/o general purpose input/output digital pin 31 pe.7 i/o general purpose input/output digital pin pb.0 i/o general purpose input/output digital pin 32 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 33 18 14 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 34 19 15 rts0 rts0: request to send output pin for uart0 pb.3 i/o general purpose input/output digital pin 35 20 16 cts0 cts0: clear to send input pin for uart0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 71 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pd.6 i/o general purpose input/output digital pin 36 21 17 canrx0 i can bus0 rx input pd.7 i/o general purpose input/output digital pin 37 22 18 cantx0 o can bus0 tx output 23 19 pd.14 i/o general purpose input/output digital pin 38 rxd2 i rxd2: data receiver input pin for uart2 24 20 pd.15 i/o general purpose input/output digital pin 39 txd2 o txd2: data transmitter output pin for uart2 pc.5 i/o general purpose input/output digital pin 40 mosi01 o mosi01: spi0 2 nd mosi (master out, slave in) pin pc.4 i/o general purpose input/output digital pin 41 miso01 i miso01: spi0 2 nd miso (master in, slave out) pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 42 25 21 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 43 26 22 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 44 27 23 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 45 28 24 i2slrcl k i/o i2slrclk: i 2 s left right channel clock 46 pe.6 i/o general purpose input/output digital pin pe.5 i/o general purpose input/output digital pin 47 29 pwm5 o pwm5: pwm output pb.11 i/o general purpose input/output digital pin 48 30 tm3 o tm3: timer3 external counter input numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 72 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pwm4 o pwm4: pwm output pb.10 i/o general purpose input/output digital pin 31 tm2 o tm2: timer2 external counter input 49 spiss01 i/o spiss01: spi0 2 nd slave select pin pb.9 i/o general purpose input/output digital pin 32 tm1 o tm1: timer1 external counter input 50 spiss11 i/o spiss11: spi1 2 nd slave select pin 51 pe.4 i/o general purpose input/output digital pin 52 pe.3 i/o general purpose input/output digital pin 53 pe.2 i/o general purpose input/output digital pin pe.1 i/o general purpose input/output digital pin 54 pwm7 o pwm7: pwm output pe.0 i/o general purpose input/output digital pin 55 pwm6 o pwm6: pwm output pc.13 i/o general purpose input/output digital pin 56 mosi11 o mosi11: spi1 2 nd mosi (master out, slave in) pin pc.12 i/o general purpose input/output digital pin 57 miso11 i miso11: spi1 2 nd miso (master in, slave out) pin pc.11 i/o general purpose input/output digital pin 58 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 59 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 60 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 61 36 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 62 37 25 i2smclk o i2smclk: i 2 s master clock output pin 63 38 26 pa.14 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 73 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pwm2 o pwm2: pwm output pa.13 i/o general purpose input/output digital pin 64 39 27 pwm1 o pwm1: pwm output pa.12 i/o general purpose input/output digital pin 65 40 28 pwm0 o pwm0: pwm output 66 41 29 ice_dat i/o serial wired debugger data pin 67 42 30 ice_ck i serial wired debugger clock pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 vss p ground 70 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 71 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 72 45 33 adc1 ai adc1: adc analog input pa.2 i/o general purpose input/output digital pin 73 46 34 adc2 ai adc2: adc analog input pa.3 i/o general purpose input/output digital pin 74 47 35 adc3 ai adc3: adc analog input pa.4 i/o general purpose input/output digital pin 75 48 36 adc4 ai adc4: adc analog input pa.5 i/o general purpose input/output digital pin 76 49 37 adc5 ai adc5: adc analog input pa.6 i/o general purpose input/output digital pin 77 50 38 adc6 ai adc6: adc analog input pa.7 i/o general purpose input/output digital pin 51 39 adc7 ai adc7: adc analog input 78 spiss21 i/o spiss21: spi2 2 nd slave select pin 79 vref ap voltage reference input for adc 80 52 40 avdd ap power supply for internal analog circuit 81 pd.0 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 74 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description spiss20 i/o spiss20: spi2 slave select pin pd.1 i/o general purpose input/output digital pin 82 spiclk2 i/o spiclk2: spi2 serial clock pin pd.2 i/o general purpose input/output digital pin 83 miso20 i miso20: spi2 miso (master in, slave out) pin pd.3 i/o general purpose input/output digital pin 84 mosi20 o mosi20: spi2 mosi (master out, slave in) pin pd.4 i/o general purpose input/output digital pin 85 miso21 i miso21: spi2 2 nd miso (master in, slave out) pin pd.5 i/o general purpose input/output digital pin 86 mosi21 o mosi21: spi2 2 nd mosi (master out, slave in) pin pc.7 i/o general purpose input/output digital pin 87 53 41 cpn0 i cpn0: comparator0 negative input pin pc.6 i/o general purpose input/output digital pin 88 54 42 cpp0 i cpp0: comparator0 positive input pin pc.15 i/o general purpose input/output digital pin 89 55 cpn1 i cpn1: comparator1 negative input pin pc.14 i/o general purpose input/output digital pin 90 56 cpp1 i cpp1: comparator1 positive input pin pb.15 i/o general purpose input/output digital pin 91 57 43 /int1 i /int1: external interrupt0 input pin 92 58 44 xt1_out o external 4~24 mhz crystal output pin 93 59 45 xt1_in i external 4~24 mhz crystal input pin 94 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 ps2dat i/o ps2 data pin 98 ps2clk i/o ps2 clock pin 99 63 47 pvss p pll ground numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 75 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 100 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 76 - revision v1.06 3.6.1.4 numicro ? nuc140 medium density pin description pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 1 pe.15 i/o general purpose input/output digital pin 2 pe.14 i/o general purpose input/output digital pin 3 pe.13 i/o general purpose input/output digital pin pb.14 i/o general purpose input/output digital pin /int0 i /int0: external interrupt1 input pin 4 1 spiss31 i/o spiss31: spi3 2 nd slave select pin pb.13 i/o general purpose input/output digital pin 5 2 cpo1 o comparator1 output pin pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 6 3 1 clko o frequency divider output pin 7 4 2 x32o o external 32.768 kh z crystal output pin 8 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 9 6 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin pa.10 i/o general purpose input/output digital pin 10 7 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin pa.9 i/o general purpose input/output digital pin 11 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 12 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pd.8 i/o general purpose input/output digital pin 13 spiss30 i/o spiss30: spi3 slave select pin pd.9 i/o general purpose input/output digital pin 14 spiclk3 i/o spiclk3: spi3 serial clock pin pd.10 i/o general purpose input/output digital pin 15 miso30 i miso30: spi3 miso (master in, slave out) pin 16 pd.11 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 77 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description mosi30 o mosi30: spi3 mosi (master out, slave in) pin pd.12 i/o general purpose input/output digital pin 17 miso31 i miso31: spi3 2 nd miso (master in, slave out) pin pd.13 i/o general purpose input/output digital pin 18 mosi31 o mosi31: spi3 2 nd mosi (master out, slave in) pin pb.4 i/o general purpose input/output digital pin 19 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 20 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 21 12 rts1 rts1: request to send output pin for uart1 pb.7 i/o general purpose input/output digital pin 22 13 cts1 cts1: clear to send input pin for uart1 23 14 10 ldo p ldo output pin 24 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 25 16 12 vss p ground 26 pe.8 i/o general purpose input/output digital pin 27 pe.7 i/o general purpose input/output digital pin 28 17 13 vbus usb power supply: from usb host or hub. 29 18 14 vdd33 usb internal power regulator output 3.3v decoupling pin 30 19 15 d- usb usb differential signal d- 31 20 16 d+ usb usb differential signal d+ pb.0 i/o general purpose input/output digital pin 32 21 17 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 33 22 18 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 34 23 rts0 rts0: request to send output pin for uart0 35 24 pb.3 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 78 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description cts0 cts0: clear to send input pin for uart0 pd.6 i/o general purpose input/output digital pin 36 25 19 canrx0 i can bus0 rx input pd.7 i/o general purpose input/output digital pin 37 26 20 cantx0 o can bus0 tx output pd.14 i/o general purpose input/output digital pin 38 27 rxd2 i rxd2: data receiver input pin for uart2 pd.15 i/o general purpose input/output digital pin 39 28 txd2 o txd2: data transmitter output pin for uart2 pc.5 i/o general purpose input/output digital pin 40 mosi01 o mosi01: spi0 2 nd mosi (master out, slave in) pin pc.4 i/o general purpose input/output digital pin 41 miso01 i miso01: spi0 2 nd miso (master in, slave out) pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 42 29 21 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 43 30 22 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 44 31 23 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 45 32 24 i2slrcl k i/o i2slrclk: i 2 s left right channel clock 46 pe.6 i/o general purpose input/output digital pin pe.5 i/o general purpose input/output digital pin 47 pwm5 o pwm5: pwm output 48 pb.11 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 79 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description tm3 o tm3: timer3 external counter input pwm4 o pwm4: pwm output pb.10 i/o general purpose input/output digital pin tm2 o tm2: timer2 external counter input 49 spiss01 i/o spiss01: spi0 2 nd slave select pin pb.9 i/o general purpose input/output digital pin tm1 o tm1: timer1 external counter input 50 spiss11 i/o spiss11: spi1 2 nd slave select pin 51 pe.4 i/o general purpose input/output digital pin 52 pe.3 i/o general purpose input/output digital pin 53 pe.2 i/o general purpose input/output digital pin pe.1 i/o general purpose input/output digital pin 54 pwm7 o pwm7: pwm output pe.0 i/o general purpose input/output digital pin 55 pwm6 o pwm6: pwm output pc.13 i/o general purpose input/output digital pin 56 mosi11 o mosi11: spi1 2 nd mosi (master out, slave in) pin pc.12 i/o general purpose input/output digital pin 57 miso11 i miso11: spi1 2 nd miso (master in, slave out) pin pc.11 i/o general purpose input/output digital pin 58 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 59 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 60 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin 61 36 spiss10 i/o spiss10: spi1 slave select pin pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 62 37 25 i2smclk o i2smclk: i 2 s master clock output pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 80 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pa.14 i/o general purpose input/output digital pin 63 38 26 pwm2 o pwm2: pwm output pa.13 i/o general purpose input/output digital pin 64 39 27 pwm1 o pwm1: pwm output pa.12 i/o general purpose input/output digital pin 65 40 28 pwm0 o pwm0: pwm output 66 41 29 ice_dat i/o serial wired debugger data pin 67 42 30 ice_ck i serial wired debugger clock pin 68 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 69 vss p ground 70 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 71 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 72 45 33 adc1 ai adc1: adc analog input pa.2 i/o general purpose input/output digital pin 73 46 34 adc2 ai adc2: adc analog input pa.3 i/o general purpose input/output digital pin 74 47 35 adc3 ai adc3: adc analog input pa.4 i/o general purpose input/output digital pin 75 48 36 adc4 ai adc4: adc analog input pa.5 i/o general purpose input/output digital pin 76 49 37 adc5 ai adc5: adc analog input pa.6 i/o general purpose input/output digital pin 77 50 38 adc6 ai adc6: adc analog input pa.7 i/o general purpose input/output digital pin 39 adc7 ai adc7: adc analog input 78 51 spiss21 i/o spiss21: spi2 2 nd slave select pin 79 vref ap voltage reference input for adc 80 52 40 avdd ap power supply for internal analog circuit numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 81 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description pd.0 i/o general purpose input/output digital pin 81 spiss20 i/o spiss20: spi2 slave select pin pd.1 i/o general purpose input/output digital pin 82 spiclk2 i/o spiclk2: spi2 serial clock pin pd.2 i/o general purpose input/output digital pin 83 miso20 i miso20: spi2 miso (master in, slave out) pin pd.3 i/o general purpose input/output digital pin 84 mosi20 o mosi20: spi2 mosi (master out, slave in) pin pd.4 i/o general purpose input/output digital pin 85 miso21 i miso21: spi2 2 nd miso (master in, slave out) pin pd.5 i/o general purpose input/output digital pin 86 mosi21 o mosi21: spi2 2 nd mosi (master out, slave in) pin pc.7 i/o general purpose input/output digital pin 87 53 41 cpn0 i cpn0: comparator0 negative input pin pc.6 i/o general purpose input/output digital pin 88 54 42 cpp0 i cpp0: comparator0 positive input pin pc.15 i/o general purpose input/output digital pin 89 55 cpn1 i cpn1: comparator1 negative input pin pc.14 i/o general purpose input/output digital pin 90 56 cpp1 i cpp1: comparator1 positive input pin pb.15 i/o general purpose input/output digital pin 91 57 43 /int1 i /int1: external interrupt0 input pin 92 58 44 xt1_out o external 4~24 mhz crystal output pin 93 59 45 xt1_in i external 4~24 mhz crystal input pin 94 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 95 61 vss p ground 96 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 97 ps2dat i/o ps2 data pin 98 ps2clk i/o ps2 clock pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 82 - revision v1.06 pin no. lqfp 100 lqfp 64 lqfp 48 pin name pin type description 99 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 100 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 83 - revision v1.06 3.6.2 numicro ? nuc100/nuc120/nuc130/nuc140 low density pin description 3.6.2.1 numicro ? nuc100 low density pin description pin no. lqfp 64 lqfp 48 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin pb.13 i/o general purpose input/output digital pin cpo1 o comparator1 output pin 2 ad1 i/o ebi address/data bus bit1 (64pin package only) pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 1 clko o frequency divider output pin 3 ad0 i/o ebi address/data bus bit0 (64pin package only) 4 2 x32o o external 32.768 kh z crystal output pin 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin 6 nrd o ebi read enable output pin (64pin package only) pa.10 i/o general purpose input/output digital pin 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 7 nwr o ebi write enable output pin (64pin package only) pa.9 i/o general purpose input/output digital pin 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pb.4 i/o general purpose input/output digital pin 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin 12 rts1 rts1: request to send output pin for uart1 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 84 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description ale o ebi address latch enable output pin (64pin package only) pb.7 i/o general purpose input/output digital pin cts1 cts1: clear to send input pin for uart1 13 ncs o ebi chip select enable output pin (64pin package only) 14 10 ldo p ldo output pin 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 vss p ground pb.0 i/o general purpose input/output digital pin 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 18 14 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 15 rts0 rts0: request to send output pin for uart0 19 nwrl o ebi low byte write enable output pin (64pin package only) pb.3 i/o general purpose input/output digital pin 16 cts0 cts0: clear to send input pin for uart0 20 nwrh o ebi high byte write enable output pin (64pin package only) 21 pd.6 i/o general purpose input/output digital pin 22 pd.7 i/o general purpose input/output digital pin 23 pd.14 i/o general purpose input/output digital pin 24 pd.15 i/o general purpose input/output digital pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 25 17 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 26 18 i2sdi i i2sdi: i 2 s data input numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 85 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 27 19 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 28 20 i2slrclk i/o i2slrclk: i 2 s left right channel clock 29 21 pe.5 i/o general purpose input/output digital pin pb.11 i/o general purpose input/output digital pin 30 22 tm3 o tm3: timer3 external counter input pb.10 i/o general purpose input/output digital pin 31 23 tm2 o tm2: timer2 external counter input pb.9 i/o general purpose input/output digital pin 32 24 tm1 o tm1: timer1 external counter input pc.11 i/o general purpose input/output digital pin 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin spiss10 i/o spiss10: spi1 slave select pin 36 mclk o ebi external clock output pin (64pin package only) pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 26 pwm2 o pwm2: pwm output 38 ad15 i/o ebi address/data bus bit15 (64pin package only) pa.13 i/o general purpose input/output digital pin 39 27 pwm1 o pwm1: pwm output numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 86 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description ad14 i/o ebi address/data bus bit14 (64pin package only) pa.12 i/o general purpose input/output digital pin 28 pwm0 o pwm0: pwm output 40 ad13 i/o ebi address/data bus bit13 (64pin package only) 41 29 ice_dat i/o serial wired debugger data pin 42 30 ice_ck i serial wired debugger clock pin 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 33 adc1 ai adc1: adc analog input 45 ad12 i/o ebi address/data bus bit12 (64pin package only) pa.2 i/o general purpose input/output digital pin 34 adc2 ai adc2: adc analog input 46 ad11 i/o ebi address/data bus bit11 (64pin package only) pa.3 i/o general purpose input/output digital pin 35 adc3 ai adc3: adc analog input 47 ad10 i/o ebi address/data bus bit10 (64pin package only) pa.4 i/o general purpose input/output digital pin 36 adc4 ai adc4: adc analog input 48 ad9 i/o ebi address/data bus bit9 (64pin package only) pa.5 i/o general purpose input/output digital pin 37 adc5 ai adc5: adc analog input 49 ad8 i/o ebi address/data bus bit8 (64pin package only) pa.6 i/o general purpose input/output digital pin 38 adc6 ai adc6: adc analog input 50 ad7 i/o ebi address/data bus bit7 (64pin package only) pa.7 i/o general purpose input/output digital pin 39 adc7 ai adc7: adc analog input 51 ad6 i/o ebi address/data bus bit6 (64pin package only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 87 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description 52 40 avdd ap power supply for internal analog circuit pc.7 i/o general purpose input/output digital pin 41 cpn0 i cpn0: comparator0 negative input pin 53 ad5 i/o ebi address/data bus bit5 (64pin package only) pc.6 i/o general purpose input/output digital pin 42 cpp0 i cpp0: comparator0 positive input pin 54 ad4 i/o ebi address/data bus bit4 (64pin package only) pc.15 i/o general purpose input/output digital pin cpn1 i cpn1: comparator1 negative input pin 55 ad3 i/o ebi address/data bus bit3 (64pin package only) pc.14 i/o general purpose input/output digital pin cpp1 i cpp1: comparator1 positive input pin 56 ad2 i/o ebi address/data bus bit2 (64pin package only) pb.15 i/o general purpose input/output digital pin 57 43 /int1 i /int1: external interrupt0 input pin 58 44 xt1_out o external 4~24 mhz crystal output pin 59 45 xt1_in i external 4~24 mhz crystal input pin 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 61 vss p ground 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 88 - revision v1.06 3.6.2.2 numicro ? nuc120 low density pin description pin no. lqfp 64 lqfp 48 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin pb.13 i/o general purpose input/output digital pin cpo1 o comparator1 output pin 2 ad1 i/o ebi address/data bus bit1 (64pin package only) pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 1 clko o frequency divider output pin 3 ad0 i/o ebi address/data bus bit0 (64pin package only) 4 2 x32o o external 32.768 kh z crystal output pin 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin 6 nrd o ebi read enable output pin (64pin package only) pa.10 i/o general purpose input/output digital pin 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 7 nwr o ebi write enable output pin (64pin package only) pa.9 i/o general purpose input/output digital pin 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pb.4 i/o general purpose input/output digital pin 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin rts1 rts1: request to send output pin for uart1 12 ale o ebi address latch enabl e output pin (64pin package only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 89 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pb.7 i/o general purpose input/output digital pin cts1 cts1: clear to send input pin for uart1 13 ncs o ebi chip select enable output pin (64pin package only) 14 10 ldo p ldo output pin 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 vss p ground 17 13 vbus usb power supply: from usb host or hub. 18 14 vdd33 usb internal power regulator output 3.3v decoupling pin 19 15 d- usb usb differential signal d- 20 16 d+ usb usb differential signal d+ pb.0 i/o general purpose input/output digital pin 21 17 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 22 18 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 19 rts0 rts0: request to send output pin for uart0 23 nwrl o ebi low byte write enable output pin (64pin package only) pb.3 i/o general purpose input/output digital pin 20 cts0 cts0: clear to send input pin for uart0 24 nwrh o ebi high byte write enable output pin (64pin package only) pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 25 21 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 26 22 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin 27 23 spiclk0 i/o spiclk0: spi0 serial clock pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 90 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 28 24 i2slrclk i/o i2slrclk: i 2 s left right channel clock 29 pe.5 i/o general purpose input/output digital pin pb.11 i/o general purpose input/output digital pin 30 tm3 o tm3: timer3 external counter input pb.10 i/o general purpose input/output digital pin 31 tm2 o tm2: timer2 external counter input pb.9 i/o general purpose input/output digital pin 32 tm1 o tm1: timer1 external counter input pc.11 i/o general purpose input/output digital pin 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin spiss10 i/o spiss10: spi1 slave select pin 36 mclk o ebi external clock output pin (64pin package only) pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 26 pwm2 o pwm2: pwm output 38 ad15 i/o ebi address/data bus bit15 (64pin package only) pa.13 i/o general purpose input/output digital pin 27 pwm1 o pwm1: pwm output 39 ad14 i/o ebi address/data bus bit14 (64pin package only) 40 28 pa.12 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 91 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pwm0 o pwm0: pwm output ad13 i/o ebi address/data bus bit13 (64pin package only) 41 29 ice_dat i/o serial wired debugger data pin 42 30 ice_ck i serial wired debugger clock pin 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 33 adc1 ai adc1: adc analog input 45 ad12 i/o ebi address/data bus bit12 (64pin package only) pa.2 i/o general purpose input/output digital pin 34 adc2 ai adc2: adc analog input 46 ad11 i/o ebi address/data bus bit11 (64pin package only) pa.3 i/o general purpose input/output digital pin 35 adc3 ai adc3: adc analog input 47 ad10 i/o ebi address/data bus bit10 (64pin package only) pa.4 i/o general purpose input/output digital pin 36 adc4 ai adc4: adc analog input 48 ad9 i/o ebi address/data bus bit9 (64pin package only) pa.5 i/o general purpose input/output digital pin 37 adc5 ai adc5: adc analog input 49 ad8 i/o ebi address/data bus bit8 (64pin package only) pa.6 i/o general purpose input/output digital pin 38 adc6 ai adc6: adc analog input 50 ad7 i/o ebi address/data bus bit7 (64pin package only) pa.7 i/o general purpose input/output digital pin 39 adc7 ai adc7: adc analog input 51 ad6 i/o ebi address/data bus bit6 (64pin package only) 52 40 avdd ap power supply for internal analog circuit 53 41 pc.7 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 92 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description cpn0 i cpn0: comparator0 negative input pin ad5 i/o ebi address/data bus bit5 (64pin package only) pc.6 i/o general purpose input/output digital pin 42 cpp0 i cpp0: comparator0 positive input pin 54 ad4 i/o ebi address/data bus bit4 (64pin package only) pc.15 i/o general purpose input/output digital pin cpn1 i cpn1: comparator1 negative input pin 55 ad3 i/o ebi address/data bus bit3 (64pin package only) pc.14 i/o general purpose input/output digital pin cpp1 i cpp1: comparator1 positive input pin 56 ad2 i/o ebi address/data bus bit2 (64pin package only) pb.15 i/o general purpose input/output digital pin 57 43 /int1 i /int1: external interrupt0 input pin 58 44 xt1_out o external 4~24 mhz crystal output pin 59 45 xt1_in i external 4~24 mhz crystal input pin 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 61 vss p ground 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 93 - revision v1.06 3.6.2.3 numicro ? nuc130 low density pin description pin no. lqfp 64 lqfp 48 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin pb.13 i/o general purpose input/output digital pin cpo1 o comparator1 output pin 2 ad1 i/o ebi address/data bus bit1 (64pin package only) pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 1 clko o frequency divider output pin 3 ad0 i/o ebi address/data bus bit0 (64pin package only) 4 2 x32o o external 32.768 kh z crystal output pin 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin 6 nrd o ebi read enable output pin (64pin package only) pa.10 i/o general purpose input/output digital pin 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 7 nwr o ebi write enable output pin (64pin package only) pa.9 i/o general purpose input/output digital pin 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pb.4 i/o general purpose input/output digital pin 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin rts1 rts1: request to send output pin for uart1 12 ale o ebi address latch enable output pin (64pin package only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 94 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pb.7 i/o general purpose input/output digital pin cts1 cts1: clear to send input pin for uart1 13 ncs o ebi chip select enable output pin (64pin package only) 14 10 ldo p ldo output pin 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 vss p ground pb.0 i/o general purpose input/output digital pin 17 13 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 18 14 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin 15 rts0 rts0: request to send output pin for uart0 19 nwrl o ebi low byte write enable output pin (64pin package only) pb.3 i/o general purpose input/output digital pin 16 cts0 cts0: clear to send input pin for uart0 20 nwrh o ebi high byte write enable output pin (64pin package only) pd.6 i/o general purpose input/output digital pin 21 17 canrx0 i can bus0 rx input pd.7 i/o general purpose input/output digital pin 22 18 cantx0 o can bus0 tx output 23 19 pd.14 i/o general purpose input/output digital pin 24 20 pd.15 i/o general purpose input/output digital pin pc.3 i/o general purpose input/output digital pin mosi00 o mosi00: spi0 mosi (master out, slave in) pin 25 21 i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 26 22 i2sdi i i2sdi: i 2 s data input numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 95 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 27 23 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 28 24 i2slrclk i/o i2slrclk: i 2 s left right channel clock 29 pe.5 i/o general purpose input/output digital pin pb.11 i/o general purpose input/output digital pin 30 tm3 o tm3: timer3 external counter input pb.10 i/o general purpose input/output digital pin 31 tm2 o tm2: timer2 external counter input pb.9 i/o general purpose input/output digital pin 32 tm1 o tm1: timer1 external counter input pc.11 i/o general purpose input/output digital pin 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin spiss10 i/o spiss10: spi1 slave select pin 36 mclk o ebi external clock output pin (64pin package only) pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 26 pwm2 o pwm2: pwm output 38 ad15 i/o ebi address/data bus bit15 (64pin package only) 39 27 pa.13 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 96 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pwm1 o pwm1: pwm output ad14 i/o ebi address/data bus bit14 (64pin package only) pa.12 i/o general purpose input/output digital pin 28 pwm0 o pwm0: pwm output 40 ad13 i/o ebi address/data bus bit13 (64pin package only) 41 29 ice_dat i/o serial wired debugger data pin 42 30 ice_ck i serial wired debugger clock pin 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 33 adc1 ai adc1: adc analog input 45 ad12 i/o ebi address/data bus bit12 (64pin package only) pa.2 i/o general purpose input/output digital pin 34 adc2 ai adc2: adc analog input 46 ad11 i/o ebi address/data bus bit11 (64pin package only) pa.3 i/o general purpose input/output digital pin 35 adc3 ai adc3: adc analog input 47 ad10 i/o ebi address/data bus bit10 (64pin package only) pa.4 i/o general purpose input/output digital pin 36 adc4 ai adc4: adc analog input 48 ad9 i/o ebi address/data bus bit9 (64pin package only) pa.5 i/o general purpose input/output digital pin 37 adc5 ai adc5: adc analog input 49 ad8 i/o ebi address/data bus bit8 (64pin package only) pa.6 i/o general purpose input/output digital pin 38 adc6 ai adc6: adc analog input 50 ad7 i/o ebi address/data bus bit7 (64pin package only) pa.7 i/o general purpose input/output digital pin 51 39 adc7 ai adc7: adc analog input numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 97 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description ad6 i/o ebi address/data bus bit6 (64pin package only) 52 40 avdd ap power supply for internal analog circuit pc.7 i/o general purpose input/output digital pin 41 cpn0 i cpn0: comparator0 negative input pin 53 ad5 i/o ebi address/data bus bit5 (64pin package only) pc.6 i/o general purpose input/output digital pin 42 cpp0 i cpp0: comparator0 positive input pin 54 ad4 i/o ebi address/data bus bit4 (64pin package only) pc.15 i/o general purpose input/output digital pin cpn1 i cpn1: comparator1 negative input pin 55 ad3 i/o ebi address/data bus bit3 (64pin package only) pc.14 i/o general purpose input/output digital pin cpp1 i cpp1: comparator1 positive input pin 56 ad2 i/o ebi address/data bus bit2 (64pin package only) pb.15 i/o general purpose input/output digital pin 57 43 /int1 i /int1: external interrupt0 input pin 58 44 xt1_out o external 4~24 mhz crystal output pin 59 45 xt1_in i external 4~24 mhz crystal input pin 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 61 vss p ground 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 98 - revision v1.06 3.6.2.4 numicro ? nuc140 low density pin description pin no. lqfp 64 lqfp 48 pin name pin type description pb.14 i/o general purpose input/output digital pin 1 /int0 i /int0: external interrupt1 input pin pb.13 i/o general purpose input/output digital pin cpo1 o comparator1 output pin 2 ad1 i/o ebi address/data bus bit1 (64pin package only) pb.12 i/o general purpose input/output digital pin cpo0 o comparator0 output pin 1 clko o frequency divider output pin 3 ad0 i/o ebi address/data bus bit0 (64pin package only) 4 2 x32o o external 32.768 kh z crystal output pin 5 3 x32i i external 32.768 khz crystal input pin pa.11 i/o general purpose input/output digital pin 4 i2c1scl i/o i2c1scl: i 2 c1 clock pin 6 nrd o ebi read enable output pin (64pin package only) pa.10 i/o general purpose input/output digital pin 5 i2c1sda i/o i2c1sda: i 2 c1 data input/output pin 7 nwr o ebi write enable output pin (64pin package only) pa.9 i/o general purpose input/output digital pin 8 6 i2c0scl i/o i2c0scl: i 2 c0 clock pin pa.8 i/o general purpose input/output digital pin 9 7 i2c0sda i/o i2c0sda: i 2 c0 data input/output pin pb.4 i/o general purpose input/output digital pin 10 8 rxd1 i rxd1: data receiver input pin for uart1 pb.5 i/o general purpose input/output digital pin 11 9 txd1 o txd1: data transmitter output pin for uart1 pb.6 i/o general purpose input/output digital pin rts1 rts1: request to send output pin for uart1 12 ale o ebi address latch enable output pin (64pin package only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 99 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pb.7 i/o general purpose input/output digital pin cts1 cts1: clear to send input pin for uart1 13 ncs o ebi chip select enable output pin (64pin package only) 14 10 ldo p ldo output pin 15 11 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 vss p ground 17 13 vbus usb power supply: from usb host or hub. 18 14 vdd33 usb internal power regulator output 3.3v decoupling pin 19 15 d- usb usb differential signal d- 20 16 d+ usb usb differential signal d+ pb.0 i/o general purpose input/output digital pin 21 17 rxd0 i rxd0: data receiver input pin for uart0 pb.1 i/o general purpose input/output digital pin 22 18 txd0 o txd0: data transmitter output pin for uart0 pb.2 i/o general purpose input/output digital pin rts0 rts0: request to send output pin for uart0 23 nwrl o ebi low byte write enable output pin (64pin package only) pb.3 i/o general purpose input/output digital pin cts0 cts0: clear to send input pin for uart0 24 nwrh o ebi high byte write enable output pin (64pin package only) pd.6 i/o general purpose input/output digital pin 25 19 canrx0 i can bus0 rx input pd.7 i/o general purpose input/output digital pin 26 20 cantx0 o can bus0 tx output 27 pd.14 i/o general purpose input/output digital pin 28 pd.15 i/o general purpose input/output digital pin 29 21 pc.3 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 100 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description mosi00 o mosi00: spi0 mosi (master out, slave in) pin i2sdo o i2sdo: i 2 s data output pc.2 i/o general purpose input/output digital pin miso00 i miso00: spi0 miso (master in, slave out) pin 30 22 i2sdi i i2sdi: i 2 s data input pc.1 i/o general purpose input/output digital pin spiclk0 i/o spiclk0: spi0 serial clock pin 31 23 i2sbclk i/o i2sbclk: i 2 s bit clock pin pc.0 i/o general purpose input/output digital pin spiss00 i/o spiss00: spi0 slave select pin 32 24 i2slrclk i/o i2slrclk: i 2 s left right channel clock pc.11 i/o general purpose input/output digital pin 33 mosi10 o mosi10: spi1 mosi (master out, slave in) pin pc.10 i/o general purpose input/output digital pin 34 miso10 i miso10: spi1 miso (master in, slave out) pin pc.9 i/o general purpose input/output digital pin 35 spiclk1 i/o spiclk1: spi1 serial clock pin pc.8 i/o general purpose input/output digital pin spiss10 i/o spiss10: spi1 slave select pin 36 mclk o ebi external clock output pin (64pin package only) pa.15 i/o general purpose input/output digital pin pwm3 o pwm3: pwm output pin 37 25 i2smclk o i2smclk: i 2 s master clock output pin pa.14 i/o general purpose input/output digital pin 26 pwm2 o pwm2: pwm output 38 ad15 i/o ebi address/data bus bit15 (64pin package only) pa.13 i/o general purpose input/output digital pin 27 pwm1 o pwm1: pwm output 39 ad14 i/o ebi address/data bus bit14 (64pin package only) 40 28 pa.12 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 101 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description pwm0 o pwm0: pwm output ad13 i/o ebi address/data bus bit13 (64pin package only) 41 29 ice_dat i/o serial wired debugger data pin 42 30 ice_ck i serial wired debugger clock pin 43 31 avss ap ground pin for analog circuit pa.0 i/o general purpose input/output digital pin 44 32 adc0 ai adc0: adc analog input pa.1 i/o general purpose input/output digital pin 33 adc1 ai adc1: adc analog input 45 ad12 i/o ebi address/data bus bit12 (64pin package only) pa.2 i/o general purpose input/output digital pin 34 adc2 ai adc2: adc analog input 46 ad11 i/o ebi address/data bus bit11 (64pin package only) pa.3 i/o general purpose input/output digital pin 35 adc3 ai adc3: adc analog input 47 ad10 i/o ebi address/data bus bit10 (64pin package only) pa.4 i/o general purpose input/output digital pin 36 adc4 ai adc4: adc analog input 48 ad9 i/o ebi address/data bus bit9 (64pin package only) pa.5 i/o general purpose input/output digital pin 37 adc5 ai adc5: adc analog input 49 ad8 i/o ebi address/data bus bit8 (64pin package only) pa.6 i/o general purpose input/output digital pin 38 adc6 ai adc6: adc analog input 50 ad7 i/o ebi address/data bus bit7 (64pin package only) pa.7 i/o general purpose input/output digital pin 39 adc7 ai adc7: adc analog input 51 ad6 i/o ebi address/data bus bit6 (64pin package only) 52 40 avdd ap power supply for internal analog circuit 53 41 pc.7 i/o general purpose input/output digital pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 102 - revision v1.06 pin no. lqfp 64 lqfp 48 pin name pin type description cpn0 i cpn0: comparator0 negative input pin ad5 i/o ebi address/data bus bit5 (64pin package only) pc.6 i/o general purpose input/output digital pin 42 cpp0 i cpp0: comparator0 positive input pin 54 ad4 i/o ebi address/data bus bit4 (64pin package only) pc.15 i/o general purpose input/output digital pin cpn1 i cpn1: comparator1 negative input pin 55 ad3 i/o ebi address/data bus bit3 (64pin package only) pc.14 i/o general purpose input/output digital pin cpp1 i cpp1: comparator1 positive input pin 56 ad2 i/o ebi address/data bus bit2 (64pin package only) pb.15 i/o general purpose input/output digital pin 57 43 /int1 i /int1: external interrupt0 input pin 58 44 xt1_out o external 4~24 mhz crystal output pin 59 45 xt1_in i external 4~24 mhz crystal input pin 60 46 /reset i external reset input: low active, set this pin low reset chip to initial stat e. with internal pull-up. 61 vss p ground 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 63 47 pvss p pll ground pb.8 i/o general purpose input/output digital pin stadc i stadc: adc external trigger input. 64 48 tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital outpu t; ai=analog input; p=power pin; ap=analog power numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 103 - revision v1.06 4 block diagram 4.1 numicro ? nuc1 00/nuc120/nuc130/nuc140 me dium density block diagram 4.1.1 numicro ? nuc100 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-1 numicro ? nuc100 medium density block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 104 - revision v1.06 4.1.2 numicro ? nuc120 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v usb-fs 512bram usbphy pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-2 numicro ? nuc120 medium density block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 105 - revision v1.06 4.1.3 numicro ? nuc130 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v can 0 pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-3 numicro ? nuc130 medium density block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 106 - revision v1.06 4.1.4 numicro ? nuc140 medium density block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v can 0 usb-fs 512bram usbphy pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-4 numicro ? nuc140 medium density block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 107 - revision v1.06 4.2 numicro ? nuc1 00/nuc120/nuc130/nuc140 low density block diagram 4.2.1 numicro ? nuc100 low density block diagram figure 4-5 numicro ? nuc100 low density block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 108 - revision v1.06 4.2.2 numicro ? nuc120 low density block diagram flash 64kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 8kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m usb-fs 512bram spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr usbphy peripherals with pdma i2s p l l ldo 2.5v~ 5.5v 10 khz 32.768 khz 22.1184 mhz 4~24 mhz figure 4-6 numicro ? nuc120 low density block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 109 - revision v1.06 4.2.3 numicro ? nuc130 low density block diagram flash 64kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 8kb gpio a,b,c,d,e uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s p l l ldo 2.5v~ 5.5v can 0 10 khz 32.768 khz 22.1184 mhz 4~24 mhz figure 4-7 numicro ? nuc130 low density block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 110 - revision v1.06 4.2.4 numicro ? nuc140 low density block diagram flash 64kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 8kb gpio a,b,c,d uart 1 -115k i2c 1 -1m timer 2/3 rtc wdt i2c 0 -1m spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v can 0 usb-fs 512bram usbphy figure 4-8 numicro ? nuc140 low density block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 111 - revision v1.06 5 functional description 5.1 arm ? cortex?-m0 core the cortex?-m0 processor is a configurable, mult istage, 32-bit risc processor. it has an amba ahb-lite interface and includes an nvic co mponent. it also has optional hardware debug functionality. the processor can execute thum b code and is compatible with other cortex-m profile processor. the profile supports two modes -thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 5-1 shows the functional controll er of processor. cortex-m0 processor core nested vectored interrupt controller (nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port (dap) debug cortex-m0 processor cortex-m0 components wakeup interrupt controller (wic) interrupts serial wire or jtag debug port ahb-lite interface figure 5-1 functional controller diagram the implemented device provides: z a low gate count processor that features: ? the armv6-m thumb? instruction set ? thumb-2 technology ? armv6-m compliant 24 -bit systick timer ? a 32-bit hardware multiplier ? the system interface supports little-endian data accesses ? the ability to have deterministic, fixed-latency, interrupt handling ? load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling ? c application binary interface compliant exception model. this is the armv6-m, c application binary interface (c-abi) compliant exception model that enables the use of pure c functions as interrupt handlers ? low power sleep-mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or the return from interrupt sleep-on-exit feature numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 112 - revision v1.06 z nvic that features: ? 32 external interrupt inputs, each with four levels of priority ? dedicated non-maskable interrupt (nmi) input. ? support for both level-sensitive and pulse-sensitive interrupt lines ? wake-up interrupt controller (wic), pr oviding ultra-low power sleep mode support. z debug support ? four hardware breakpoints. ? two watchpoints. ? program counter sampling register (pcs r) for non-intrusive code profiling. ? single step and vector catch capabilities. z bus interfaces: ? single 32-bit amba-3 ahb-lite system inte rface that provides simple integration to all system peripherals and memory. ? single 32-bit slave port that supports the dap (debug access port). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 113 - revision v1.06 5.2 system manager 5.2.1 overview system management includes these following sections: z system resets z system memory map z system management registers for part number id, chip reset and on-chip controllers reset , multi-functional pin control z system timer (systick) z nested vectored interrupt controller (nvic) z system control registers 5.2.2 system reset the system reset can be issued by one of the below listed events. for these reset event flags can be read by rstrc register. z the power-on reset z the low level on the /reset pin z watchdog time out reset z low voltage reset z brown-out detector reset z cpu reset z system reset system reset and power-on reset all reset the whole chip including all peripherals. the difference between system reset and power-on reset is external crystal circuit and ispcon.bs bit. system reset doesn?t reset external crystal circuit and ispcon.bs bit, but power-on reset does. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 114 - revision v1.06 5.2.3 system power distribution in this chip, the power distribution is divided into three segments. z analog power from avdd and avss prov ides the power fo r analog components operation. z digital power from vdd and vss supplies th e power to the internal regulator which provides a fixed 2.5v power for digital operation and i/o pins. z usb transceiver power from vbus offe rs the power for operating the usb transceiver. (for numicro ? nuc120/nuc140 only) the outputs of internal voltage regulators, ldo and vdd33, require an external capacitor which should be located close to the corresponding pin. figure 5-2 shows the po wer dist ribution of numicro ? nuc120/nuc140 and figure 5-3 shows the power distribution of numicro ? nuc100/ nu c130 vdd vss x32o x32i pvss figure 5-2 numicro ? nuc120/nuc140 power distribution diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 115 - revision v1.06 5v to 2.5v ldo pll 12-bit sar-adc brown out detector por50 por25 low voltage reset external 32.768 khz crystal analog comparator temperature seneor flash digital logic 2.5v internal 22.1184 mhz & 10 khz oscillator avdd avss vdd vss ldo 10uf io cell gpio x32o x32i pvss nuc100/ nuc130 power distribution figure 5-3 numicro ? nuc100/ nuc130 power distribution diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 116 - revision v1.06 5.2.4 system memory map numicro ? nuc100 series provides 4g-byte addressi ng space. the memory locations assigned to each on-chip controllers are shown in the fo llowing table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on- chip peripherals. numicro ? nuc100 series only supports little-endian data format. address space token controllers flash & sram memory space 0x0000_0000 ? 0x0001_ffff flash_ba flash memory space (128kb) 0x2000_0000 ? 0x2000_3fff sram_ba sram memory space (16kb) 0x6000_0000 ? 0x6001_ffff extmem_ba external memory space (128kb) (low density 64-pin only) ahb controllers space (0x5000_0000 ? 0x501f_ffff) 0x5000_0000 ? 0x5000_01ff gcr_ba syst em global control registers 0x5000_0200 ? 0x5000_02ff clk_ba clock control registers 0x5000_0300 ? 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 ? 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 ? 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 ? 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 ? 0x5001_03ff ebi_ba external bus interface control registers (low density 64-pin only) apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 ? 0x4000_7fff wdt_ba wa tchdog timer control registers 0x4000_8000 ? 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 ? 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 ? 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 ? 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 ? 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 ? 0x4004_3fff pwma_ba pwm0/1/2/3 control registers 0x4005_0000 ? 0x4005_3fff uart0_ba uart0 control registers numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 117 - revision v1.06 0x4006_0000 ? 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400d_0000 ? 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 ? 0x400e_ffff adc_ba analog-digital-converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 ? 0x4010_3fff ps2_ba ps2 interface control registers 0x4011_0000 ? 0x4011_3fff tmr23_ba timer2/timer3 control registers 0x4012_0000 ? 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 ? 0x4013_3fff spi2_ba spi2 with master/slave function control registers (medium density only) 0x4013_4000 ? 0x4013_7fff spi3_ba spi3 with master/slave function control registers (medium density only) 0x4014_0000 ? 0x4014_3fff pwmb_ba pwm4/5/6/7 control registers (medium density only) 0x4015_0000 ? 0x4015_3fff uart1_ba uart1 control registers 0x4015_4000 ? 0x4015_7fff uart2_ba uart2 control registers (medium density only) 0x4018_0000 ? 0x4018_3fff can0_ba can0 bus control registers 0x401a_0000 ? 0x401a_3fff i2s_ba i 2 s interface control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 ? 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 ? 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 ? 0xe000_ed8f scs_ba system control registers table 5-1 address space assignments for on-chip controllers numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 118 - revision v1.06 5.2.5 system manager control registers r : read only, w : write only, r/w : both read and write register offset r/w description reset value gcr_ba = 0x5000_0000 pdid gcr_ba+0x00 r part device identification number register 0x0014_0018 [1] rstsrc gcr_ba+0x04 r/w system reset source register 0x0000_00xx iprstc1 gcr_ba+0x08 r/w ip reset control register1 0x0000_0000 iprstc2 gcr_ba+0x0c r/w ip reset control register2 0x0000_0000 cpr gcr_ba+0x10 r/w high performance mode register (low density only) 0x0000_0000 bodcr gcr_ba+0x18 r/w brown out detector control register 0x0000_008x tempcr gcr_ba+0x1c r/w temperature sensor control register 0x0000_0000 porcr gcr_ba+0x24 r/w power-on-reset controller register 0x0000_00xx gpa_mfp gcr_ba+0x30 r/w gpioa multiple function and input type control register 0x0000_0000 gpb_mfp gcr_ba+0x34 r/w gpiob multiple function and input type control register 0x0000_0000 gpc_mfp gcr_ba+0x38 r/w gpioc multiple function and input type control register 0x0000_0000 gpd_mfp gcr_ba+0x3c r/w gpiod multiple function and input type control register 0x0000_0000 gpe_mfp gcr_ba+0x40 r/w gpioe multiple function and input type control register 0x0000_0000 alt_mfp gcr_ba+0x50 r/w alternative multiple function pin control register 0x0000_0000 regwrprot gcr_ba+0x100 r/w register wr ite protect register 0x0000_0000 note: [1] dependents on part number. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 119 - revision v1.06 part device id code register (pdid) register offset r/w description reset value pdid gcr_ba+0x00 r part device identification number register 0x0014_0018 [1] [1] every part number has a unique default reset value. 31 30 29 28 27 26 25 24 part number [31:24] 23 22 21 20 19 18 17 16 part number [23:16] 15 14 13 12 11 10 9 8 part number [15:8] 7 6 5 4 3 2 1 0 part number [7:0] bits descriptions [31:0] pdid part device identification number this register reflects device part number code . s/w can read this register to identify which device is used. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 120 - revision v1.06 system reset source register (rstsrc) this register provides specific information for softw are to identify this chip?s reset source from last operation. register offset r/w description reset value rstsrc gcr_ba+0x04 r/w system reset source register 0x0000_00xx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rsts_cpu reserved rsts_sys rsts_bod rsts_lvr rsts_wdt rsts_rese t rsts_por bits descriptions [31:8] reserved reserved [7] rsts_cpu the rsts_cpu flag is set by hardware if software writes cpu_rst (iprstc1[1]) 1 to reset cortex-m0 cpu kernel and flash memory controller (fmc). 1 = the cortex-m0 cpu kernel and fmc are reset by software setting cpu_rst to 1. 0 = no reset from cpu software can write 1 to clear this bit to zero. [6] reserved reserved [5] rsts_sys the rsts_sys flag is set by the ?reset signal ? from the cortex_m0 kernel to indicate the previous reset source. 1 = the cortex_m0 had issued the reset signal to reset the system by software writing 1 to bit sysresetreq(aircr[2], application interrupt and reset control register, address = 0xe000ed0c) in system control registers of cortex_m0 kernel. 0 = no reset from cortex_m0 software can write 1 to clear this bit to zero. [4] rsts_bod the rsts_bod flag is set by the ?reset signal? from the brown-out-detector to indicate the previous reset source. 1 = the bod had issued the reset signal to reset the system 0 = no reset from bod software can write 1 to clear this bit to zero. [3] rsts_lvr the rsts_lvr flag is set by the ?reset signal? from the low-voltage-reset controller to indicate the previous reset source. 1 = the lvr controller had issued the reset signal to reset the system. 0 = no reset from lvr numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 121 - revision v1.06 software can write 1 to clear this bit to zero. [2] rsts_wdt the rsts_wdt flag is set by the ?reset signal ? from the watchdog timer to indicate the previous reset source. 1 = the watchdog timer had issued the reset signal to reset the system. 0 = no reset from watchdog timer software can write 1 to clear this bit to zero. [1] rsts_reset the rsts_reset flag is set by the ?reset signal? from the /reset pin to indicate the previous reset source. 1 = the pin /reset had issued the reset signal to reset the system. 0 = no reset from /reset pin software can write 1 to clear this bit to zero. [0] rsts_por the rsts_por flag is set by the ?reset signal? from the power-on reset (por) controller or bit chip_rst (iprstc1[0]) to indicate the previous reset source. 1 = the power-on reset (por) or chip_rst had issued the reset signal to reset the system. 0 = no reset from por or chip_rst software can write 1 to clear this bit to zero. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 122 - revision v1.06 peripheral reset control register1 (iprstc1) register offset r/w description reset value iprstc1 gcr_ba+0x08 r/w ip reset control register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ebi_rst pdma_rst cpu_rst chip_rst bits descriptions [31:4] reserved reserved [3] ebi_rst ebi controller reset (low density 64 pin package only) (write-protection bit in nuc100/nuc120/nuc130/nuc140 low density 64-pin package) set this bit to 1 will generate a reset signal to the ebi. user need to set this bit to 0 to release from the reset state. this bit is the protected bit, it means progra mming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100 1 = ebi controller reset 0 = ebi controller normal operation [2] pdma_rst pdma controller reset (write-protection bit in nuc100/nuc120/nuc130/nuc140 low density) setting this bit to 1 will generate a reset signal to the pdma. user need to set this bit to 0 to release from reset state. this bit is the protected bit, it means progra mming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. 1 = pdma controller reset 0 = pdma controller normal operation [1] cpu_rst cpu kernel one shot reset (write-protection bit) setting this bit will only reset the cpu kern el and flash memory controller(fmc), and this bit will automatically return to 0 after the 2 clock cycles this bit is the protected bit, it means progr amming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100 1 = cpu one shot reset 0 = cpu normal operation [0] chip_rst chip one shot reset (write-protection bit) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 123 - revision v1.06 setting this bit will reset the whole chip, in cluding cpu kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. the chip_rst is same as the por reset, all the chip controllers is reset and the chip setting from flash are also reload. about the difference between chip_rst and sysresetreq, please refer to section 5.2.2 this bit is the protected bit. it means progra mming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100 1 = chip one shot reset 0 = chip normal operation numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 124 - revision v1.06 peripheral reset control register2 (iprstc2) setting these bits 1 will generate asynchronous reset signals to the corresponding ip controller. users need to set these bits to 0 to releas e corresponding ip controller from reset state register offset r/w description reset value iprstc2 gcr_ba+0x0c r/w peripheral controller reset control register 2 0x0000_0000 31 30 29 28 27 26 25 24 reserved i2s_rst adc_rst usbd_rst reserved can0_rst 23 22 21 20 19 18 17 16 ps2_rst acmp_rst pwm47_rst pwm03_rst reserved uart2_rst uart1_rst uart0_rst 15 14 13 12 11 10 9 8 spi3_rst spi2_rst spi1_rst spi0_rst reserved i2c1_rst i2c0_rst 7 6 5 4 3 2 1 0 reserved tmr3_rst tmr2_rst tmr1_rst tmr0_rst gpio_rst reserved bits descriptions [31:30] reserved reserved [29] i2s_rst i 2 s controller reset 1 = i 2 s controller reset 0 = i 2 s controller normal operation [28] adc_rst adc controller reset 1 = adc controller reset 0 = adc controller normal operation [27] usbd_rst usb device controller reset 1 = usb device controller reset 0 = usb device controller normal operation [26:25] reserved reserved [24] can0_rst can0 controller reset 1 = can0 controller reset 0 = can0 controller normal operation [23] ps2_rst ps2 controller reset 1 = ps2 controller reset 0 = ps2 controller normal operation [22] acmp_rst analog comparator controller reset 1 = analog comparator controller reset 0 = analog comparator controller normal operation [21] pwm47_rst pwm47 controller reset (medium density only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 125 - revision v1.06 1 = pwm47 controller reset 0 = pwm47 controller normal operation [20] pwm03_rst pwm03 controller reset 1 = pwm03 controller reset 0 = pwm03 controller normal operation [19] reserved reserved [18] uart2_rst uart2 controller reset (medium density only) 1 = uart2 controller reset 0 = uart2 controller normal operation [17] uart1_rst uart1 controller reset 1 = uart1 controller reset 0 = uart1 controller normal operation [16] uart0_rst uart0 controller reset 1 = uart0 controller reset 0 = uart0 controller normal operation [15] spi3_ rst spi3 controller reset (medium density only) 1 = spi3 controller reset 0 = spi3 controller normal operation [14] spi2_ rst spi2 controller reset (medium density only) 1 = spi2 controller reset 0 = spi2 controller normal operation [13] spi1_ rst spi1 controller reset 1 = spi1 controller reset 0 = spi1 controller normal operation [12] spi0_ rst spi0 controller reset 1 = spi0 controller reset 0 = spi0 controller normal operation [11:10] reserved reserved [9] i2c1_rst i2c1 controller reset 1 = i 2 c1 controller reset 0 = i 2 c1 controller normal operation [8] i2c0_rst i2c0 controller reset 1 = i 2 c0 controller reset 0 = i 2 c0 controller normal operation [7:6] reserved reserved [5] tmr3_rst timer3 controller reset 1 = timer3 controller reset 0 = timer3 controller normal operation [4] tmr2_rst timer2 controller reset numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 126 - revision v1.06 1 = timer2 controller reset 0 = timer2 controller normal operation [3] tmr1_rst timer1 controller reset 1 = timer1 controller reset 0 = timer1 controller normal operation [2] tmr0_rst timer0 controller reset 1 = timer0 controller reset 0 = timer0 controller normal operation [1] gpio_rst gpio controller reset 1 = gpio controller reset 0 = gpio controller normal operation [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 127 - revision v1.06 high performance mode register (cpr) this register is used to control chip performance (low density only) register offset r/w description reset value cpr gcr_ba+0x10 r/w high performance mode register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved hpe bits descriptions [31:1] reversed reserved [0] hpe high performance enable (write-protection bit) this bit is used to control chip operation performance. when this bit set, internal ram and gpio access is working with zero wait state, flash controller will predict next address more efficiently. the high performance is enabled without limiting by chip operation frequency. 1 = chip operation at high performance mode 0 = chip operation at normal mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 128 - revision v1.06 brown-out detector control register (bodcr) partial of the bodcr control registers values are initiated by the flash configuration and partial bits are write-protected bit. programming write-prot ected bits needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regi ster protection. reference the register regwrprot at address gcr_ba+0x100 register offset r/w description reset value bodcr gcr_ba+0x18 r/w brown out detector control register 0x0000_008x 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 lvr_en bod_out bod_lpm bod_intf bod_rsten bod_vl bod_en bits descriptions [31:8] reserved reserved [7] lvr_en low voltage reset enable (write-protection bit) the lvr function reset the chip when the i nput power voltage is lower than lvr circuit setting. lvr function is enabled in default. 1 = enabled low voltage reset function ? after enabling the bit, the lvr function will be active with 100us delay for lvr output stable. (default). 0 = disabled low voltage reset function this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100 [6] bod_out brown out detector output status 1 = brown out detector output status is 1. it means the detected voltage is lower than bod_vl setting. if the bod_en is 0, bod f unction disabled , this bit always responds 0 0 = brown out detector output status is 0. it means the detected voltage is higher than bod_vl setting or bod_en is 0 [5] bod_lpm brown out detector low power mode (write-protection bit) 1 = enable the bod low power mode 0 = bod operate in normal mode (default) the bod consumes about 100ua in normal mode, the low power mode can reduce the current to about 1/10 but slow the bod response. this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 129 - revision v1.06 regwrprot at address gcr_ba+0x100. [4] bod_intf brown out detector interrupt flag 1 = when brown out detector detects the vdd is dropped down through the voltage of bod_vl setting or the vdd is raised up through the voltage of bod_vl setting, this bit is set to 1 and the brown out interrupt is requested if brown out interrupt is enabled. 0 = brown out detector does not detect any voltage draft at vdd down through or up through the voltage of bod_vl setting. software can write 1 to clear this bit to zero. [3] bod_rsten brown out reset enable (write-protection bit) 1 = enable the brown out ?reset? function while the brown out detector function is enabled (bod_en high) and bod reset function is enabled (bod_rsten high), bod wi ll assert a signal to reset chip when the detected voltage is lower than the threshold (bod_out high). 0 = enable the brown out ?interrupt? function while the bod function is enabled (bod_e n high) and bod interrupt function is enabled (bod_rsten low), bod will assert an interrupt if bod_out is high. bod interrupt will keep till to the bod_en set to 0. bod interrupt can be blocked by disabling the nvic bod interrupt or di sabling bod function (set bod_en low). the default value is set by flash controller us er configuration register config0 bit[20]. this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. [2:1] bod_vl brown out detector threshold voltage selection (write-protection bits) the default value is set by flash controller us er configuration register config0 bit[22:21] this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. bov_vl[1] bov_vl[0] brown out voltage 1 1 4.5v 1 0 3.8v 0 1 2.7v 0 0 2.2v [0] bod_en brown out detector enable (write-protection bit) the default value is set by flash controller us er configuration register config0 bit[23] 1 = brown out detector function is enabled 0 = brown out detector function is disabled this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 130 - revision v1.06 temperature sensor control register (tempcr) register offset r/w description reset value tempcr gcr_ba+0x1c r/w temperature sensor control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved vtemp_en bits descriptions [31:1] reserved reserved [0] vtemp_en temperature sensor enable this bit is used to enable/disabl e temperature sensor function. 1 = enabled temperature sensor function 0 = disabled temperature s ensor function (default) after this bit is set to 1, the value of te mperature can get from adc conversion result by adc channel selecting channel 7 and alternative multiplexer channel selecting temperature sensor. detail adc conversi on function please refe rence adc function chapter. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 131 - revision v1.06 power-on-reset control register (porcr) register offset r/w description reset value porcr gcr_ba+0x24 r/w power-on-reset controller register 0x0000_00xx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 por_dis_code[15:8] 7 6 5 4 3 2 1 0 por_dis_code[7:0] bits descriptions [31:16] reserved reserved [15:0] por_dis_code the register is used for the power-on-reset enable control (write-protection bits) when power on, the por circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the por active again. user can disable internal por circuit to avoid unpredictable noise to cause chip reset by writing 0x5aa5 to this field. the por function will be active again when this field is set to another value or chip is reset by other reset source, including: /reset, watch dog, lvr reset, bod reset, ice reset command and the software-chip reset function this bit is the protected bit. it means progr amming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 132 - revision v1.06 multiple function pin gpioa con trol register (gpa_mfp) register offset r/w description reset value gpa_mfp gcr_ba+0x30 r/w gpioa multiple function and input type control register 0x0000_0000 31 30 29 28 27 26 25 24 gpa_type[15:8] 23 22 21 20 19 18 17 16 gpa_type[7:0] 15 14 13 12 11 10 9 8 gpa_mfp[15:8] 7 6 5 4 3 2 1 0 gpa_mfp[7:0] bits descriptions [31:16] gpa_typen 1 = enable gpioa[15:0] i/o i nput schmitt trigger function 0 = disable gpioa[15:0] i/o in put schmitt trigger function [15] gpa_mfp15 pa.15 pin function selection the pin function depends on gpa_mfp 15 and pa15_i2smclk (alt_mfp[9]). pa15_i2smclk gpa_mfp[15] pa.15 function x 0 gpio 0 1 pwm3 (pwm) 1 1 i2smclk (i 2 s) [14] gpa_mfp14 pa.14 pin function selection the pin function depends on gpa_mfp14 and ebi_hb_en[7] (alt_mfp[23]) and ebi_en (alt_mfp[11]). ebi_hb_en[7] ebi_en gpa_mfp[14] pa.14 function x x 0 gpio x 0 1 pwm2 (pwm) 0 1 1 pwm2 (pwm) 1 1 1 ad15 (ebi ad bus bit 15) [13] gpa_mfp13 pa.13 pin function selection the pin function depends on gpa_mfp13 and ebi_hb_en[6] (alt_mfp[22]) and ebi_en (alt_mfp[11]). ebi_hb_en[6] ebi_en gpa_mfp[13] pa.13 function x x 0 gpio x 0 1 pwm1 (pwm) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 133 - revision v1.06 0 1 1 pwm1 (pwm) 1 1 1 ad14 (ebi ad bus bit 14) [12] gpa_mfp12 pa.12 pin function selection the pin function depends on gpa_mfp12 and ebi_hb_en[5] (alt_mfp[21]) and ebi_en (alt_mfp[11]). ebi_hb_en[5] ebi_en gpa_mfp[12] pa.12 function x x 0 gpio x 0 1 pwm0 (pwm) 0 1 1 pwm0 (pwm) 1 1 1 ad13 (ebi ad bus bit 13) [11] gpa_mfp11 pa.11 pin function selection the pin function depends on gpa_mf p11 and ebi_en (alt_mfp[11]). ebi_en gpa_mfp[11] pa.11 function x 0 gpio 0 1 scl1 (i 2 c) 1 1 nrd (ebi) [10] gpa_mfp10 pa.10 pin function selection the pin function depends on gpa_mf p10 and ebi_en (alt_mfp[11]). ebi_en gpa_mfp[10] pa.10 function x 0 gpio 0 1 sda1 (i 2 c) 1 1 nwr (ebi) [9] gpa_mfp9 pa.9 pin function selection 1 = the i 2 c0 scl function is selected to the pin pa.9 0 = the gpioa[9] is selected to the pin pa.9 [8] gpa_mfp8 pa.8 pin function selection 1 = the i 2 c0 sda function is selected to the pin pa.8 0 = the gpioa[8] is selected to the pin pa.8 [7] gpa_mfp7 pa.7 pin function selection the pin function depends on gpa_mfp7 and pa7_s21 (alt_mfp[2]) and ebi_en (alt_mfp[11]). ebi_en pa7_s21 gpa_mfp[7] pa.7 function x x 0 gpio 0 0 1 adc7 (adc) 0 1 1 spiss21 (spi2) 1 x 1 ad6 (ebi ad bus bit 6) [6] gpa_mfp6 pa.6 pin function selection the pin function depends on gpa_mfp6 and ebi_en (alt_mfp[11]). numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 134 - revision v1.06 ebi_en gpa_mfp[6] pa.6 function x 0 gpio 0 1 adc6 (adc) 1 1 ad7 (ebi ad bus bit 7) [5] gpa_mfp5 pa.5 pin function selection the pin function depends on gpa_mfp5 and ebi_hb_en[0] (alt_mfp[16]) and ebi_en (alt_mfp[11]). ebi_hb_en[0] ebi_en gpa_mfp[5] pa.5 function x x 0 gpio x 0 1 adc5 (adc) 0 1 1 adc5 (adc) 1 1 1 ad8 (ebi ad bus bit 8) [4] gpa_mfp4 pa.4 pin function selection the pin function depends on gpa_mfp4 and ebi_hb_en[1] (alt_mfp[17]) and ebi_en (alt_mfp[11]). ebi_hb_en[1] ebi_en gpa_mfp[4] pa.4 function x x 0 gpio x 0 1 adc4 (adc) 0 1 1 adc4 (adc) 1 1 1 ad9 (ebi ad bus bit 9) [3] gpa_mfp3 pa.3 pin function selection the pin function depends on gpa_mfp3 and ebi_hb_en[2] (alt_mfp[18]) and ebi_en (alt_mfp[11]). ebi_hb_en[2] ebi_en gpa_mfp[3] pa.3 function x x 0 gpio x 0 1 adc3 (adc) 0 1 1 adc3 (adc) 1 1 1 ad10 (ebi ad bus bit 10) [2] gpa_mfp2 pa.2 pin function selection the pin function depends on gpa_mfp2 and ebi_hb_en[3] (alt_mfp[19]) and ebi_en (alt_mfp[11]). ebi_hb_en[3] ebi_en gpa_mfp[2] pa.2 function x x 0 gpio x 0 1 adc2 (adc) 0 1 1 adc2 (adc) 1 1 1 ad11 (ebi ad bus bit 11) [1] gpa_mfp1 pa.1 pin function selection the pin function depends on gpa_mfp1 and ebi_hb_en[4] (alt_mfp[20]) and numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 135 - revision v1.06 ebi_en (alt_mfp[11]). ebi_hb_en[4] ebi_en gpa_mfp[1] pa.1 function x x 0 gpio x 0 1 adc1 (adc) 0 1 1 adc1 (adc) 1 1 1 ad12 (ebi ad bus bit 12) [0] gpa_mfp0 pa.0 pin function selection 1 = the adc0 (analog-to-digital converter channel 0) function is selected to the pin pa.0 0 = the gpioa[0] is selected to the pin pa.0 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 136 - revision v1.06 multiple function pin gpiob con trol register (gpb_mfp) register offset r/w description reset value gpb_mfp gcr_ba+0x34 r/w gpiob multiple function and input type control register 0x0000_0000 31 30 29 28 27 26 25 24 gpb_type[15:8] 23 22 21 20 19 18 17 16 gpb_type[7:0] 15 14 13 12 11 10 9 8 gpb_mfp[15:8] 7 6 5 4 3 2 1 0 gpb_mfp[7:0] bits descriptions [31:16] gpb_typen 1 = enable gpiob[15:0] i/o i nput schmitt trigger function 0 = disable gpiob[15:0] i/o in put schmitt trigger function [15] gpb_mfp15 pb.15 pin function selection 1 = the external interrupt int1 function is selected to the pin pb.15 0 = the gpiob[15] is selected to the pin pb.15 [14] gpb_mfp14 pb.14 pin function selection the pin function depends on gpb_mf p14 and pb14_s31 (alt_mfp[3]) pb14_s31 gpb_mfp[14] pb.14 function x 0 gpio 0 1 /int0 1 1 spiss31 (spi3) [13] gpb_mfp13 pb.13 pin function selection the pin function depends on gpb_mf p13 and ebi_en (alt_mfp[11]). ebi_en gpb_mfp[13] pb.13 function x 0 gpio 0 1 cpo1 (cmp) 1 1 ad1 (ebi ad bus bit 1) [12] gpb_mfp12 pb.12 pin function selection the pin function depends on gpb_mfp12 and pb12_clko (alt_mfp[10]) and ebi_en (alt_mfp[11]). ebi_en pb12_clko gpb_mfp[12] pb.12 function numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 137 - revision v1.06 x x 0 gpio 0 0 1 cpo0 (cmp) 0 1 1 clko (clock driver output) 1 x 1 ad0 (ebi ad bus bit 0) [11] gpb_mfp11 pb.11 pin function selection the pin function depends on gpb_mfp11 and pb11_pwm4 (alt_mfp[4]). pb11_pwm4 gpb_mfp[11] pb.11 function x 0 gpio 0 1 tm3 1 1 pwm4 (pwm) [10] gpb_mfp10 pb.10 pin function selection the pin function depends on gpb_mf p10 and pb10_s01 (alt_mfp[0]). pb10_s01 gpb_mfp[10] pb.10 function x 0 gpio 0 1 tm2 1 1 spiss01 (spi0) [9] gpb_mfp9 pb.9 pin function selection the pin function depends on gpb_mfp9 and pb9_s11 (alt_mfp[1]). pb9_s11 gpb_mfp[9] pb.9 function x 0 gpio 0 1 tm1 1 1 spiss11 (spi1) [8] gpb_mfp8 pb.8 pin function selection 1 = the tm0 (timer/counter external trigger clock input) function is selected to the pin pb.8 0 = the gpiob[8] is selected to the pin pb.8 [7] gpb_mfp7 pb.7 pin function selection the pin function depends on gpb_mfp7 and ebi_en (alt_mfp[11]). ebi_en gpb_mfp[7] pb.7 function x 0 gpio 0 1 cts1 (uart1) 1 1 ncs (ebi) [6] gpb_mfp6 pb.6 pin function selection the pin function depends on gpb_mfp6 and ebi_en (alt_mfp[11]). ebi_en gpb_mfp[6] pb.6 function x 0 gpio numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 138 - revision v1.06 0 1 rts1 (uart1) 1 1 ale (ebi) [5] gpb_mfp5 pb. 5 pin function selection 1 = the uart1 txd function is selected to the pin pb.5 0 = the gpiob[5] is selected to the pin pb.5 [4] gpb_mfp4 pb.4 pin function selection 1 = the uart1 rxd function is selected to the pin pb.4 0 = the gpiob[4] is selected to the pin pb.4 [3] gpb_mfp3 pb.3 pin function selection the pin function depends on gpb_mfp3 and ebi_nwrh_en (alt_mfp[14]) and ebi_en (alt_mfp[11]). ebi_nwrh_en ebi_en gpb_mfp[3] pb.3 function x x 0 gpio x 0 1 cts0 (uart0) 0 1 1 cts0 (uart0) 1 1 1 nwrh (ebi write high byte enable) [2] gpb_mfp2 pb.2 pin function selection the pin function depends on gpb_mfp2 and ebi_nwrl_en (alt_mfp[13]) and ebi_en (alt_mfp[11]). ebi_nwrl_en ebi_en gpb_mfp[2] pb.2 function x x 0 gpio x 0 1 rts0 (uart0) 0 1 1 rts0 (uart0) 1 1 1 nwrl (ebi write low byte enable) [1] gpb_mfp1 pb.1 pin function selection 1 = the uart0 txd function is selected to the pin pb.1 0 = the gpiob[1] is selected to the pin pb.1 [0] gpb_mfp0 pb.0 pin function selection 1 = the uart0 rxd function is selected to the pin pb.0 0 = the gpiob[0] is selected to the pin pb.0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 139 - revision v1.06 multiple function pin gpioc con trol register (gpc_mfp) register offset r/w description reset value gpc_mfp gcr_ba+0x38 r/w gpioc multiple function and input type control register 0x0000_0000 31 30 29 28 27 26 25 24 gpc_type[15:8] 23 22 21 20 19 18 17 16 gpc_type[7:0] 15 14 13 12 11 10 9 8 gpc_mfp[15:8] 7 6 5 4 3 2 1 0 gpc_mfp[7:0] bits descriptions [31:16] gpc_typen 1 = enable gpioc[n] i/o inpu t schmitt trigger function 0 = disable gpioc[n] i/o i nput schmitt trigger function [15] gpc_mfp15 pc.15 pin function selection the pin function depends on gpc_mf p15 and ebi_en (alt_mfp[11]). ebi_en gpc_mfp[15] pc.15 function x 0 gpio 0 1 cpn1 (cmp) 1 1 ad3 (ebi ad bus bit 3) [14] gpc_mfp14 pc.14 pin function selection the pin function depends on gpc_mf p14 and ebi_en (alt_mfp[11]). ebi_en gpc_mfp[14] pc.14 function x 0 gpio 0 1 cpp1 (cmp) 1 1 ad2 (ebi ad bus bit 2) [13] gpc_mfp13 pc.13 pin function selection 1 = the spi1 mosi1 (master output, slave input pin-1) function is selected to the pin pc.13 0 = the gpioc[13] is selected to the pin pc.13 [12] gpc_mfp12 pc.12 pin function selection 1 = the spi1 miso1 (master input, slave output pin-1) function is selected to the pin pc.12 0 = the gpioc[12] is selected to the pin pc.12 [11] gpc_mfp11 pc.11 pin function selection numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 140 - revision v1.06 1 = the spi1 mosi0 (master output, slave input pin-0) function is selected to the pin pc.11 0 = the gpioc[11] is selected to the pin pc.11 [10] gpc_mfp10 pc.10 pin function selection 1 = the spi1 miso0 (master input, slave output pin-0) function is selected to the pin pc.10 0 = the gpioc[10] is selected to the pin pc.10 [9] gpc_mfp9 pc.9 pin function selection 1 = the spi1 spiclk function is selected to the pin pc.9 0 = the gpioc[9] is selected to the pin pc.9 [8] gpc_mfp8 pc.8 pin function selection the pin function depends on gpc_mfp8 and ebi_mclk_en (alt_mfp[12]) and ebi_en (alt_mfp[11]). ebi_mclk_en ebi_en gpc_mfp[8] pc.8 function x x 0 gpio x 0 1 spiss10 (spi1) 0 1 1 spiss10 (spi1) 1 1 1 mclk (ebi clock output) [7] gpc_mfp7 pc.7 pin function selection the pin function depends on gpc_mfp7 and ebi_en (alt_mfp[11]). ebi_en gpc_mfp[7] pc.7 function x 0 gpio 0 1 cpn0 (cmp) 1 1 ad5 (ebi ad bus bit 5) [6] gpc_mfp6 pc.6 pin function selection the pin function depends on gpc_mfp6 and ebi_en (alt_mfp[11]). ebi_en gpc_mfp[6] pc.6 function x 0 gpio 0 1 cpp0 (cmp) 1 1 ad4 (ebi ad bus bit 4) [5] gpc_mfp5 pc.5 pin function selection 1 = the spi0 mosi1 (master output, slave input pin-1) function is selected to the pin pc.5 0 = the gpioc[5] is selected to the pin pc.5 [4] gpc_mfp4 pc.4 pin function selection 1 = the spi0 miso1 (master input, slave output pin-1) function is selected to the pin pc.4 0 = the gpioc[4] is selected to the pin pc.4 [3] gpc_mfp3 pc.3 pin function selection bits pc2_i2sdo (alt_mfp[8]) and gpc_ mfp[3] determine the pc.3 function. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 141 - revision v1.06 pc2_i2sdo gpc_mfp[3] pc.3 function x 0 gpio 0 1 mosi00 (spi0) 1 1 i2sdo (i 2 s) [2] gpc_mfp2 pc.2 pin function selection bits pc2_i2sdi (alt_mfp[7]) and gpc_ mfp[2] determine the pc.2 function. pc2_i2sdi gpc_mfp[2] pc.2 function x 0 gpio 0 1 miso00 (spi0) 1 1 i2sdi (i 2 s) [1] gpc_mfp1 pc.1 pin function selection bits pc1_i2sbclk (alt_mfp[6]) and gpc_ mfp[1] determine the pc.1 function. pc1_i2sbclk gpc_mfp[1] pc.1 function x 0 gpio 0 1 spiclk0 (spi0) 1 1 i2sbclk (i 2 s) [0] gpc_mfp0 pc.0 pin function selection bits pc0_i2slrclk (alt_mfp[5]) and gpc_ mfp[0] determine the pc.0 function. pc0_i2slrclk gpc_mfp[0] pc.0 function x 0 gpio 0 1 spiss00 (spi0) 1 1 i2slrclk (i 2 s) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 142 - revision v1.06 multiple function pin gpiod con trol register (gpd_mfp) register offset r/w description reset value gpd_mfp gcr_ba+0x3c r/w gpiod multiple function and input type control register 0x0000_0000 31 30 29 28 27 26 25 24 gpd_type[15:8] 23 22 21 20 19 18 17 16 gpd_type[7:0] 15 14 13 12 11 10 9 8 gpd_mfp[15:8] 7 6 5 4 3 2 1 0 gpd_mfp[7:0] bits descriptions [31:16] gpd_typen 1 = enable gpiod[15:0] i/o i nput schmitt trigger function 0 = disable gpiod[15:0] i/o in put schmitt trigger function [15] gpd_mfp15 pd.15 pin function selection (medium density only) 1 = the uart2 txd function is selected to the pin pd.15 0 = the gpiod[15] selected to the pin pd.15 [14] gpd_mfp14 pd.14 pin function selection (medium density only) 1 = the uart2 rxd function is selected to the pin pd.14 0 = the gpiod[14] selected to the pin pd.14 [13] gpd_mfp13 pd.13 pin function selection (medium density only) 1 = the spi3 mosi1 (master output, slave input pin-1) function is selected to the pin pd.13 0 = the gpiod[13] is selected to the pin pd.13 [12] gpd_mfp12 pd.12 pin function selection (medium density only) 1 = the spi3 miso1 (master input, slave output pin-1) function is selected to the pin pd.12 0 = the gpiod[12] is selected to the pin pd.12 [11] gpd_mfp11 pd.11 pin function selection (medium density only) 1 = the spi3 mosi0 (master output, slave input pin-0) function is selected to the pin pd.11 0 = the gpiod[11] is selected to the pin pd.11 [10] gpd_mfp10 pd.10 pin function selection (medium density only) 1 = the spi3 miso0 (master input, slave output pin-0) function is selected to the pin pd.10 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 143 - revision v1.06 0 = the gpiod[10] is selected to the pin pd.10 [9] gpd_mfp9 pd.9 pin function selection (medium density only) 1 = the spi3 spiclk function is selected to the pin pd.9 0 = the gpiod[9] is selected to the pin pd.9 [8] gpd_mfp8 pd.8 pin function selection (medium density only) 1 = the spi3 ss30 function is selected to the pin pd8 0 = the gpiod[8] is selected to the pin pd8 [7] gpd_mfp7 pd.7 pin function selection (medium density only) 1 = the can0 tx function is selected to the pin pd.7 0 = the gpiod[7] is selected to the pin pd.7 [6] gpd_mfp6 pd.6 pin function selection (medium density only) 1 = the can0 rx function is selected to the pin pd.6 0 = the gpiod[6] is selected to the pin pd.6 [5] gpd_mfp5 pd.5 pin function selection (medium density only) 1 = the spi2 mosi1 (master output, slave input pin-1) function is selected to the pin pd.5 0 = the gpiod[5] is selected to the pin pd.5 [4] gpd_mfp4 pd.4 pin function selection (medium density only) 1 = the spi2 miso1 (master input, slave output pin-1) function is selected to the pin pd.4 0 = the gpiod[4]is selected to the pin pd.4 [3] gpd_mfp3 pd.3 pin function selection for nuc100/nuc120/nuc130/nuc140 medium density 1 = the spi2 mosi0 (master output, slave input pin-0) function is selected to the pin pd.3 0 = the gpiod[3] is selected to the pin pd.3 for nuc100/nuc120/nuc130/nuc140 low density reserved [2] gpd_mfp2 pd.2 pin function selection for nuc100/nuc120/nuc130/nuc140 medium density 1 = the spi2 miso0 (master input, slave output pin-0) function is selected to the pin pd.2 0 = the gpiod[2] is selected to the pin pd.2 for nuc100/nuc120/nuc130/nuc140 low density reserved [1] gpd_mfp1 pd.1 pin function selection for nuc100/nuc120/nuc130/nuc140 medium density 1 = the spi2 spiclk function is selected to the pin pd.1 0 = the gpiod[1] is selected to the pin pd.1 for nuc100/nuc120/nuc130/nuc140 low density reserved [0] gpd_mfp0 pd.0 pin function selection (medium density only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 144 - revision v1.06 1 = the spi2 ss20 function is selected to the pin pd.0 0 = the gpiod[0] is selected to the pin pd.0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 145 - revision v1.06 multiple function pin gpioe control regis ter (gpe_mfp) register offset r/w description reset value gpe_mfp gcr_ba+0x40 r/w gpioe multiple function and input type control register 0x0000_0000 in this register, low density only has gpe_type5 register bit 31 30 29 28 27 26 25 24 gpe_type[15:8] 23 22 21 20 19 18 17 16 gpe_type[7:0] 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved gpe_mfp5 reserved gpe_mfp1 gpe_mfp0 bits descriptions [31:16] gpe_typen 1 = enable gpioe[15:0] i/o i nput schmitt trigger function 0 = disable gpioe[15:0] i/o in put schmitt trigger function note: in this field, low density only has gpe_type5 bit [15:6] reserved reserved [5] gpe_mfp5 pe.5 pin function selection (medium density only) 1 = the pwm5 function is selected to the pin pe.5 0 = the gpioe[5] is selected to the pin pe.5 [4:2] reserved reserved [1] gpe_mfp1 pe.1 pin function selection (medium density only) 1 = the pwm7 function is selected to the pin pe.1 0 = the gpioe[1] is selected to the pin pe.1 [0] gpe_mfp0 pe.0 pin function selection (medium density only) 1 = the pwm6 function is selected to the pin pe.0 0 = the gpioe[0] is selected to the pin pe.0 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 146 - revision v1.06 alternative multiple function pin control register (alt_mfp) register offset r/w description reset value alt_mfp gcr_ba+0x50 r/w alternative multiple function pin control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 ebi_hb_en 15 14 13 12 11 10 9 8 reserved ebi_nwrh_e n ebi_nwrl_e n ebi_mclk_e n ebi_en pb12_clko pa15_i2smc lk pc3_i2sdo 7 6 5 4 3 2 1 0 pc2_i2sdi pc1_i2sbcl k pc0_i2slrc lk pb11_pwm4 pb14_s31 pa7_s21 pb9_s11 pb10_s01 bits descriptions [31:24] reserved reserved [23] ebi_hb_en[7] ebi_hb_en is use to switch gpio function to ebi address/data bus high byte (ad[15:8]), ebi_hb_en, ebi_en and corresponding gpx_mfp[y] determine the px.y function. bits ebi_hb_en[7], ebi_en and gpa_mfp[14] determine the pa.14 function. ebi_hb_en[7] ebi_en gpa_mfp[14] pa.14 function x x 0 gpio x 0 1 pwm2 (pwm) 0 1 1 pwm2 (pwm) 1 1 1 ad15 (ebi ad bus bit 15) [22] ebi_hb_en[6] bits ebi_hb_en[6], ebi_en and gpa_mfp[13] determine the pa.13 function. ebi_hb_en[6] ebi_en gpa_mfp[13] pa.13 function x x 0 gpio x 0 1 pwm1 (pwm) 0 1 1 pwm1 (pwm) 1 1 1 ad14 (ebi ad bus bit 14) [21] ebi_hb_en[5] bits ebi_hb_en[5], ebi_en and gpa_mfp[12] determine the pa.12 function. ebi_hb_en[5] ebi_en gpa_mfp[12] pa.12 function x x 0 gpio x 0 1 pwm0 (pwm) 0 1 1 pwm0 (pwm) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 147 - revision v1.06 1 1 1 ad13 (ebi ad bus bit 13) [20] ebi_hb_en[4] bits ebi_hb_en[4], ebi_en and gpa_mfp[1] determine the pa.1 function. ebi_hb_en[4] ebi_en gpa_mfp[1] pa.1 function x x 0 gpio x 0 1 adc1 (adc) 0 1 1 adc1 (adc) 1 1 1 ad12 (ebi ad bus bit 12) [19] ebi_hb_en[3] bits ebi_hb_en[3], ebi_en and gpa_mfp[2] determine the pa.2 function. ebi_hb_en[3] ebi_en gpa_mfp[2] pa.2 function x x 0 gpio x 0 1 adc2 (adc) 0 1 1 adc2 (adc) 1 1 1 ad11 (ebi ad bus bit 11) [18] ebi_hb_en[2] bits ebi_hb_en[2], ebi_en and gpa_mfp[3] determine the pa.3 function. ebi_hb_en[2] ebi_en gpa_mfp[3] pa.3 function x x 0 gpio x 0 1 adc3 (adc) 0 1 1 adc3 (adc) 1 1 1 ad10 (ebi ad bus bit 10) [17] ebi_hb_en[1] bits ebi_hb_en[1], ebi_en and gpa_mfp[4] determine the pa.4 function. ebi_hb_en[1] ebi_en gpa_mfp[4] pa.4 function x x 0 gpio x 0 1 adc4 (adc) 0 1 1 adc4 (adc) 1 1 1 ad9 (ebi ad bus bit 9) [16] ebi_hb_en[0] bits ebi_hb_en[0], ebi_en and gpa_mfp[5] determine the pa.5 function. ebi_hb_en[0] ebi_en gpa_mfp[5] pa.5 function x x 0 gpio x 0 1 adc5 (adc) 0 1 1 adc5 (adc) 1 1 1 ad8 (ebi ad bus bit 8) [15] reserved reserved [14] ebi_nwrh_en bits ebi_nwrh_en, ebi_en and gpb_mfp[3] determine the pb.3 function. ebi_nwrh_en ebi_en gpb_mfp[3] pb.3 function x x 0 gpio numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 148 - revision v1.06 x 0 1 cts0 (uart0) 0 1 1 cts0 (uart0) 1 1 1 nwrh (ebi write high byte enable) [13] ebi_nwrl_en bits ebi_nwrl_en, ebi_en and gpb_mf p[2] determine the pb.2 function. ebi_nwrl_en ebi_en gpb_mfp[2] pb.2 function x x 0 gpio x 0 1 rts0 (uart0) 0 1 1 rts0 (uart0) 1 1 1 nwrl (ebi write low byte enable) [12] ebi_mclk_en bits ebi_mclk_en, ebi_en and gpc_mfp[8] determine the pc.8 function. ebi_mclk_en ebi_en gpc_mfp[8] pc.8 function x x 0 gpio x 0 1 spiss10 (spi1) 0 1 1 spiss10 (spi1) 1 1 1 mclk (ebi clock output) [11] ebi_en ebi_en is use to switch gpio function to ebi function (ad[15:0], ale, re, we, cs, mclk), it need additional registers ebi_en[7:0] and ebi_mclk_en for some gpio to switch to ebi function(ad[15:8], mclk) ebi_en gpa_mfp[6] pa.6 function x 0 gpio 0 1 adc5 (adc) 1 1 ad7 (ebi ad bus bit 7) ebi_en gpa_mfp[7] pa.7 function x 0 gpio 0 1 adc7 (adc) 1 1 ad6 (ebi ad bus bit 6) ebi_en gpc_mfp[7] pc.7 function x 0 gpio 0 1 cpn0 (cmp) 1 1 ad5 (ebi ad bus bit 5) ebi_en gpc_mfp[6] pc.6 function x 0 gpio numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 149 - revision v1.06 0 1 cpp0 (cmp) 1 1 ad4 (ebi ad bus bit 4) ebi_en gpc_mfp[15] pc.15 function x 0 gpio 0 1 cpn1 (cmp) 1 1 ad3 (ebi ad bus bit 3) ebi_en gpc_mfp[14] pc.14 function x 0 gpio 0 1 cpp1 (cmp) 1 1 ad2 (ebi ad bus bit 2) ebi_en gpb_mfp[13] pb.13 function x 0 gpio 0 1 cpo1 (cmp) 1 1 ad1 (ebi ad bus bit 1) ebi_en pb12_clko gpb_mfp[12] pb.12 function x x 0 gpio 0 0 1 cpo0 (cmp) 0 1 1 clko (clock driver output) 1 1 1 ad0 (ebi ad bus bit 0) ebi_en gpa_mfp[11] pa.11 function x 0 gpio 0 1 scl1 (i 2 c) 1 1 nrd (ebi) ebi_en gpa_mfp[10] pa.10 function x 0 gpio 0 1 sda1 (i 2 c) 1 1 nwr (ebi) ebi_en gpb_mfp[6] pb.6 function numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 150 - revision v1.06 x 0 gpio 0 1 rts1 (uart1) 1 1 ale (ebi) ebi_en gpb_mfp[7] pb.7 function x 0 gpio 0 1 cts1 (uart1) 1 1 ncs (ebi) [10] pb12_clko bits pb12_clko, gpb_mfp[12] and ebi_en (alt_mfp[11]) determine the pb.12 function. ebi_en pb12_clko gpb_mfp[12] pb.12 function x x 0 gpio x 0 1 cpo0 (cmp) 0 1 1 clko (clock driver output) 1 1 1 ad0 (ebi ad bus bit 0) [9] pa15_i2smclk bits pa15_i2smclk and gpa_mfp[15] determine the pa.15 function. pa15_i2smclk gpa_mfp[15] pa.15 function x 0 gpio 0 1 pwm3 (pwm) 1 1 i2smclk (i 2 s) [8] pc3_i2sdo bits pc2_i2sdo and gpc_mfp[3] determine the pc.3 function. pc2_i2sdo gpc_mfp[3] pc.3 function x 0 gpio 0 1 mosi00 (spi0) 1 1 i2sdo (i 2 s) [7] pc2_i2sdi bits pc2_i2sdi and gpc_mfp[2] determine the pc.2 function. pc2_i2sdi gpc_mfp[2] pc.2 function x 0 gpio 0 1 miso00 (spi0) 1 1 i2sdi (i 2 s) [6] pc1_i2sbclk bits pc1_i2sbclk and gpc_mfp[1] determine the pc.1 function. pc1_i2sbclk gpc_mfp[1] pc.1 function x 0 gpio 0 1 spiclk0 (spi0) 1 1 i2sbclk (i 2 s) [5] pc0_i2slrclk bits pc0_i2slrclk and gpc_mfp[0] determine the pc.0 function. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 151 - revision v1.06 pc0_i2slrclk gpc_mfp[0] pc.0 function x 0 gpio 0 1 spiss00 (spi0) 1 1 i2slrclk (i 2 s) [4] pb11_pwm4 bits pb11_pwm4 and gpb_mfp[11] determine the pb.11 function. pb11_pwm4 gpb_mfp[11] pb.11 function x 0 gpio 0 1 tm3 1 1 pwm4 (pwm) [3] pb14_s31 bits pb14_s31 and gpb_mfp[14] determine the pb.14 function. pb14_s31 gpb_mfp[14] pb.14 function x 0 gpio 0 1 /int0 1 1 spiss31 (spi3) [2] pa7_s21 bits pa7_s21, gpa_mfp[7] and ebi_en (alt_mfp[11]).determine the pa.7 function. ebi_en pa7_s21 gpa_mfp[7] pa.7 function x x 0 gpio 0 0 1 adc7 (adc) 0 1 1 spiss21 (spi2) 1 x 1 ad6 (ebi ad bus bit 6) [1] pb9_s11 bits pb9_s11 and gpb_mfp[9] determine the pb.9 function. pb9_s11 gpb_mfp[9] pb.9 function x 0 gpio 0 1 tm1 1 1 spiss11 (spi1) [0] pb10_s01 bits pb10_s01 and gpb_mfp[10] determine the pb.10 function. pb10_s01 gpb_mfp[10] pb.10 function x 0 gpio 0 1 tm2 1 1 spiss01 (spi0) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 152 - revision v1.06 register write-protection control register (regwrprot) some of the system control registers need to be protected to avoid inadv ertent write and disturb the chip operation. these system control registers are protected a fter the power on reset till user to disable register protection. for user to progra m these protected register s, a register protection disable sequence needs to be followed by a specia l programming. the register protection disable sequence is writing the data ?59h?, ?16h? ?8 8h? to the register regwrprot address at 0x5000_0100 continuously. any different data value, different sequence or any other write to other address during these three data writing will abort the whole sequence. after the protection is disabled, user can check the protection disable bit at address 0x5000_0100 bit0, 1 is protection disable, and 0 is protection enable. then user can update the target protected register value and then write any data to the address ?0x5000_0100? to enable register protection. this register is write for disable/enable regist er protection and read for the regprotdis status register offset r/w description reset value regwrprot gcr_ba+0x100 r/w register write-pr otection control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 regwrprot[7:1] regwrprot [0] regprotdis bits descriptions [31:16] reserved reserved [7:0] regwrprot register write-protection code (write only) some write-protection registers have to be disabled the protected function by writing the sequence value ?59h?, ?16h?, ?88h? to this field. after this sequence is completed, the regprotdis bit will be set to 1 and write-protection registers can be normal write. [0] regprotdis register write-protection disable index (read only) 1 = write-protection is disabled for writing protected registers 0 = write-protection is enabled for writing protected registers. any write to the protected register is ignored. the protected registers are: iprstc1 : address 0x5000_0008 bodcr : address 0x5000_0018 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 153 - revision v1.06 porcr : address 0x5000_0024 pwrcon : address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) apbclk bit[0] : address 0x5000_0208 (bit[0] is watch dog clock enable) clksel0 : address 0x5000_0210 (for hclk and cpu stclk clock source select) clksel1 bit[1:0] : address 0x5000_0214 (for watch dog clock source select) ispcon : address 0x5000_c000 (flash isp control register) wtcr : address 0x4000_4000 fatcon : address 0x5000_c018 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 154 - revision v1.06 5.2.6 system timer (systick) the cortex-m0 includes an integrated system time r, systick. systick pr ovides a simple, 24-bit clear-on-write, decrementing, wr ap-on-zero counter with a flexible control mechanism. the counter can be used as a real time operating sy stem (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock edge, then decrement on subsequent clocks. when the counter transitions to zero, the countflag st atus bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count fr om the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintai ned with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 155 - revision v1.06 5.2.6.1 system timer control register map r : read o nly, w : write only, r/w : both read and write register offset r/w description reset value scs_ba = 0xe000_e000 syst_csr scs_ba+0x10 r/w systick contro l and status register 0x0000_0000 syst_rvr scs_ba+0x14 r/w systick re load value register 0xxxxx_xxxx syst_cvr scs_ba+0x18 r/w systick current value register 0xxxxx_xxxx numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 156 - revision v1.06 5.2.6.2 system timer control register description systick control and status syst_csr register offset r/w description reset value syst_csr scs_ba+0x10 r/w systick contro l and status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved countflag 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved clksrc tickint enable bits descriptions [31:17] reserved reserved [16] countflag returns 1 if timer counted to 0 since last time this register was read. countflag is set by a count transition from 1 to 0. countflag is cleared on read or by a write to the current value register. [15:3] reserved reserved [2] clksrc 1 = core clock used for systick. 0 = clock source is (optional ) external reference clock [1] tickint 1 = counting down to 0 will cause the systick exception to be pended. clearing the systick current value register by a register write in software will not cause systick to be pended. 0 = counting down to 0 does not cause th e systick exception to be pended. software can use countflag to determine if a count to zero has occurred. [0] enable 1 = the counter will operate in a multi-shot manner 0 = the counter is disabled numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 157 - revision v1.06 systick reload value register sy st_rvr register offset r/w description reset value syst_rvr scs_ba+0x14 r/w systick re load value register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reload[23:16] 15 14 13 12 11 10 9 8 reload[15:8] 7 6 5 4 3 2 1 0 reload[7:0] bits descriptions [31:24] reserved reserved [23:0] reload value to load into the current value register when the counter reaches 0. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 158 - revision v1.06 systick current value register sy st_cvr register offset r/w description reset value syst_cvr scs _ba+0x18 r/w systick current value register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 current [23:16] 15 14 13 12 11 10 9 8 current [15:8] 7 6 5 4 3 2 1 0 current[7:0] bits descriptions [31:24] reserved reserved [23:0] current current counter value. this is the value of the counter at the time it is sampled. the counter does not provide read-modify-write pr otection. the register is write-clear. a software write of any value will clear the regist er to 0. unsupported bits raz (see systick reload value register). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 159 - revision v1.06 5.2.7 nested vectored interrupt controller (nvic) cortex-m0 provides an interrupt c ontroller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: z nested and vectored interrupt support z automatic processor stat e saving and restoration z dynamic priority changing z reduced and deterministic interrupt latency the nvic prioritizes and handles all supported ex ceptions. all exceptions are handled in ?handler mode?. this nvic architecture su pports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will com pare the priority of t he new interrupt to the current running one?s priority. if the priority of t he new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting addr ess of the interrupt se rvice routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlat ed isr by software. while the starting address is fetched, nvic will also automatically save proc essor state including the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume t he normal execution. thus it will ta ke less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back-to-back interrupts e fficiently without the overhead of states saving and restoration and t herefore reduces delay time in switching to pending isr at the end of current isr. the nvic al so supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher prio rity interrupt request oc curs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penal ty. thus it advances the real-time capability. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 160 - revision v1.06 5.2.7.1 exception model and system interrupt map table 5-2 lists the exception model supported by numicro ? nuc10 0 series. software can set four levels of priority on some of these exceptio ns as well as on all interrupts. the highest user- configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user-configurable interrupts is ?0?. note t hat priority ?0? is treated as the fourth priority on the system, after three system except ions ?reset?, ?nmi? and ?hard fault?. exception name vector number priority reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5-2 exception model vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 0 ~ 15 - - - system exceptions 16 0 bod_out brown-out brown-out low voltage detected interrupt 17 1 wdt_int wdt watch dog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interr upt from pa[15:0]/pb[13:0] 21 5 gpcde_int gpio external interrupt from pc[15:0]/pd[15:0]/pe[15:0] 22 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt 23 7 pwmb_int pwm4~7 pwm4, pwm5, pwm6 and pwm7 interrupt 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 161 - revision v1.06 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 uart02_int uart0/2 uart0 and uart2 interrupt 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 spi3_int spi3 spi3 interrupt 34 18 i2c0_int i 2 c0 i 2 c0 interrupt 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 can0_int can0 can0 interrupt 37 21 reserved reserved reserved 38 22 reserved reserved reserved 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps2 ps2 interrupt 41 25 acmp_int acmp analog comparator-0 or comaprator-1 interrupt 42 26 pdma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 28 pwrwu_int clkc clock controller interrupt for chip wake up from power-down state 45 29 adc_int adc adc interrupt 46 30 reserved reserved reserved 47 31 rtc_int rtc real time clock interrupt table 5-3 system interrupt map numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 162 - revision v1.06 5.2.7.2 vector table whe n any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6-m, the vector table base address is fixed at 0x00000000. t he vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in t he vector table associated with exception handler entry as illustrated in previous section. vector table word offset description 0 sp_main ? the main stack pointer vector number exception entry po inter using that vector number table 5-4 vector table format 5.2.7.3 operation description nvic inte rrupts can be enabled and disabled by writing to their corresponding interrupt set- enable or interrupt clear-enable r egister bit-field. the registers use a write-1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled stat e of the corresponding interrupts. when an interrupt is disabled, interr upt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by rese t or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the se t-pending register and clear-pending register respectively. the registers use a write-1-to-en able and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear-pending register has no effect on the execut ion status of an active interrupt. nvic interrupts are prioritized by updating an 8-bi t field within a 32-bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessibl e from a block of memory in the system control space and will be described in next section. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 163 - revision v1.06 5.2.7.4 nvic control registers r : read o nly, w : write only, r/w : both read and write register offset r/w description reset value scs_ba = 0xe000_e000 nvic_iser scs_ba+0x100 r/w irq0 ~ irq31 set-enable control register 0x0000_0000 nvic_icer scs_ba+0x180 r/w irq0 ~ irq31 clear-enable control register 0x0000_0000 nvic_ispr scs_ba+0x200 r/w irq0 ~ irq31 set-pending control register 0x0000_0000 nvic_icpr scs_ba+0x280 r/w irq0 ~ irq31 clear-pending control register 0x0000_0000 nvic_ipr0 scs_ba+0x400 r/w irq0 ~ irq3 priority control register 0x0000_0000 nvic_ipr1 scs_ba+0x404 r/w irq4 ~ irq7 priority control register 0x0000_0000 nvic_ipr2 scs_ba+0x408 r/w irq8 ~ irq11 priority control register 0x0000_0000 nvic_ipr3 scs_ba+0x40c r/w irq12 ~ irq15 priority control register 0x0000_0000 nvic_ipr4 scs_ba+0x410 r/w irq16 ~ irq19 priority control register 0x0000_0000 nvic_ipr5 scs_ba+0x414 r/w irq20 ~ irq23 priority control register 0x0000_0000 nvic_ipr6 scs_ba+0x418 r/w irq24 ~ irq27 priority control register 0x0000_0000 nvic_ipr7 scs_ba+0x41c r/w irq28 ~ irq31 priority control register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 164 - revision v1.06 irq0 ~ irq31 set-enabl e control register nvic_iser register offset r/w description reset value nvic_iser scs _ba+0x100 r/w irq0 ~ irq31 set-enable control register 0x0000_0000 31 30 29 28 27 26 25 24 setena[31:24] 23 22 21 20 19 18 17 16 setena [23:16] 15 14 13 12 11 10 9 8 setena [15:8] 7 6 5 4 3 2 1 0 setena[7:0] bits descriptions [31:0] setena enable one or more interrupts within a group of 32. each bit represents an interrupt number from irq0 ~ irq31 (vector number from 16 ~ 47). writing 1 will enable the associated interrupt. writing 0 has no effect. the register reads back with the current enable state. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 165 - revision v1.06 irq0 ~ irq31 clear-enable control register (nvic_icer) register offset r/w description reset value nvic_icer scs _ba+0x180 r/w irq0 ~ irq31 clear-enable control register 0x0000_0000 31 30 29 28 27 26 25 24 clrena[31:24] 23 22 21 20 19 18 17 16 clrena [23:16] 15 14 13 12 11 10 9 8 clrena [15:8] 7 6 5 4 3 2 1 0 clrena[7:0] bits descriptions [31:0] clrena disable one or more interrupts within a group of 32. each bit represents an interrupt number from irq0 ~ irq31 (vector number from 16 ~ 47). writing 1 will disable the associated interrupt. writing 0 has no effect. the register reads back with the current enable state. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 166 - revision v1.06 irq0 ~ irq31 set-pendi n g control register nvic_ispr register offset r/w description reset value nvic_ispr scs _ba+0x200 r/w irq0 ~ irq31 set-pending control register 0x0000_0000 31 30 29 28 27 26 25 24 setpend[31:24] 23 22 21 20 19 18 17 16 setpend [23:16] 15 14 13 12 11 10 9 8 setpend [15:8] 7 6 5 4 3 2 1 0 setpend [7:0] bits descriptions [31:0] setpend writing 1 to a bit to set pending state of the associated interrupt under software control. each bit represents an interrupt number from irq0 ~ irq31 (vector number from 16 ~ 47). writing 0 has no effect. the register reads back with the current pending state. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 167 - revision v1.06 irq0 ~ irq31 clear-pending control register nvic _icpr register offset r/w description reset value nvic_icpr scs _ba+0x280 r/w irq0 ~ irq31 clear-pending control register 0x0000_0000 31 30 29 28 27 26 25 24 clrpend [31:24] 23 22 21 20 19 18 17 16 clrpend [23:16] 15 14 13 12 11 10 9 8 clrpend [15:8] 7 6 5 4 3 2 1 0 clrpend [7:0] bits descriptions [31:0] clrpend writing 1 to a bit to remove the pending state of associated interrupt under software control. each bit represents an interrupt number from irq0 ~ irq31 (vector number from 16 ~ 47). writing 0 has no effect. the register reads back with the current pending state. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 168 - revision v1.06 irq0 ~ irq3 interrupt priority register nvic_ip r0 register offset r/w description reset value nvic_ipr0 scs _ba+0x400 r/w irq0 ~ irq3 interrupt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_3 reserved 23 22 21 20 19 18 17 16 pri_2 reserved 15 14 13 12 11 10 9 8 pri_1 reserved 7 6 5 4 3 2 1 0 pri_0 reserved bits descriptions [31:30] pri_3 priority of irq3 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_2 priority of irq2 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_1 priority of irq1 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_0 priority of irq0 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 169 - revision v1.06 irq4 ~ irq7 interrupt priority register nvic_ip r1 register offset r/w description reset value nvic_ipr1 scs _ba+0x404 r/w irq4 ~ irq7 interrupt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_7 reserved 23 22 21 20 19 18 17 16 pri_6 reserved 15 14 13 12 11 10 9 8 pri_5 reserved 7 6 5 4 3 2 1 0 pri_4 reserved bits descriptions [31:30] pri_7 priority of irq7 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_6 priority of irq6 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_5 priority of irq5 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_4 priority of irq4 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 170 - revision v1.06 irq8 ~ irq11 interrupt priority register nvi c_ipr2 register offset r/w description reset value nvic_ipr2 scs _ba+0x408 r/w irq8 ~ irq11 interrupt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_11 reserved 23 22 21 20 19 18 17 16 pri_10 reserved 15 14 13 12 11 10 9 8 pri_9 reserved 7 6 5 4 3 2 1 0 pri_8 reserved bits descriptions [31:30] pri_11 priority of irq11 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_10 priority of irq10 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_9 priority of irq9 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_8 priority of irq8 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 171 - revision v1.06 irq12 ~ irq15 interrupt priority register nvic_ ipr3 register offset r/w description reset value nvic_ipr3 scs _ba+0x40c r/w irq12 ~ irq15 interr upt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_15 reserved 23 22 21 20 19 18 17 16 pri_14 reserved 15 14 13 12 11 10 9 8 pri_13 reserved 7 6 5 4 3 2 1 0 pri_12 reserved bits descriptions [31:30] pri_15 priority of irq15 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_14 priority of irq14 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_13 priority of irq13 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_12 priority of irq12 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 172 - revision v1.06 irq16 ~ irq19 interrupt priority register nvic_ ipr4 register offset r/w description reset value nvic_ipr4 scs _ba+0x410 r/w irq16 ~ irq19 interr upt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_19 reserved 23 22 21 20 19 18 17 16 pri_18 reserved 15 14 13 12 11 10 9 8 pri_17 reserved 7 6 5 4 3 2 1 0 pri_16 reserved bits descriptions [31:30] pri_19 priority of irq19 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_18 priority of irq18 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_17 priority of irq17 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_16 priority of irq16 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 173 - revision v1.06 irq20 ~ irq23 interrupt priority register nvic_ ipr5 register offset r/w description reset value nvic_ipr5 scs _ba+0x414 r/w irq20 ~ irq23 interr upt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_23 reserved 23 22 21 20 19 18 17 16 pri_22 reserved 15 14 13 12 11 10 9 8 pri_21 reserved 7 6 5 4 3 2 1 0 pri_20 reserved bits descriptions [31:30] pri_23 priority of irq23 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_22 priority of irq22 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_21 priority of irq21 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_20 priority of irq20 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 174 - revision v1.06 irq24 ~ irq27 interrupt priority register nvic_ ipr6 register offset r/w description reset value nvic_ipr6 scs _ba+0x418 r/w irq24 ~ irq27 interr upt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_27 reserved 23 22 21 20 19 18 17 16 pri_26 reserved 15 14 13 12 11 10 9 8 pri_25 reserved 7 6 5 4 3 2 1 0 pri_24 reserved bits descriptions [31:30] pri_27 priority of irq27 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_26 priority of irq26 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_25 priority of irq25 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_24 priority of irq24 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 175 - revision v1.06 irq28 ~ irq31 interrupt priority register nvic_ ipr7 register offset r/w description reset value nvic_ipr7 scs _ba+0x41c r/w irq28 ~ irq31 interr upt priority control register 0x0000_0000 31 30 29 28 27 26 25 24 pri_31 reserved 23 22 21 20 19 18 17 16 pri_30 reserved 15 14 13 12 11 10 9 8 pri_29 reserved 7 6 5 4 3 2 1 0 pri_28 reserved bits descriptions [31:30] pri_31 priority of irq31 ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_30 priority of irq30 ?0? denotes the highest priority and ?3? denotes lowest priority [21:16] reserved reserved [15:14] pri_29 priority of irq29 ?0? denotes the highest priority and ?3? denotes lowest priority [13:8] reserved reserved [7:6] pri_28 priority of irq28 ?0? denotes the highest priority and ?3? denotes lowest priority [5:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 176 - revision v1.06 5.2.7.5 interrupt source control re gisters besides the interrupt control registers associated with the nvic, numicro ? nuc100 series also implement some specific control registers to fac ilitate the interrupt functi ons, including ?interrupt source identification?, ?nmi source selection? and ?interrupt test mode?. they are described as below. r : read only, w : write only, r/w : both read and write register offset r/w description reset value int_ba = 0x5000_0300 irq0_src int_ba+0x00 r irq0 (bod) interrupt source identity 0xxxxx_xxxx irq1_src int_ba+0x04 r irq1 (wdt) interrupt source identity 0xxxxx_xxxx irq2_src int_ba+0x08 r irq2 ((eint0) interrupt source identity 0xxxxx_xxxx irq3_src int_ba+0x0c r irq3 (eint1) interrupt source identity 0xxxxx_xxxx irq4_src int_ba+0x10 r irq4 (gpa/b) interrupt source identity 0xxxxx_xxxx irq5_src int_ba+0x14 r irq5 (gpc/d/e) interrupt source identity 0xxxxx_xxxx irq6_src int_ba+0x18 r irq6 (pwma) interrupt source identity 0xxxxx_xxxx irq7_src int_ba+0x1c r irq7 (pwmb) interrupt source identity 0xxxxx_xxxx irq8_src int_ba+0x20 r irq8 (tmr0) interrupt source identity 0xxxxx_xxxx irq9_src int_ba+0x24 r irq9 (tmr1) interrupt source identity 0xxxxx_xxxx irq10_src int_ba+0x28 r irq10 (tmr2) inte rrupt source identity 0xxxxx_xxxx irq11_src int_ba+0x2c r irq11 (tmr3) in terrupt source identity 0xxxxx_xxxx irq12_src int_ba+0x30 r irq12 (urt0) inte rrupt source identity 0xxxxx_xxxx irq13_src int_ba+0x34 r irq13 (urt1) inte rrupt source identity 0xxxxx_xxxx irq14_src int_ba+0x38 r irq14 (spi0) inte rrupt source identity 0xxxxx_xxxx irq15_src int_ba+0x3c r irq15 (spi1) in terrupt source identity 0xxxxx_xxxx irq16_src int_ba+0x40 r irq16 (spi2) inte rrupt source identity 0xxxxx_xxxx irq17_src int_ba+0x44 r irq17 (spi3)) inte rrupt source identity 0xxxxx_xxxx irq18_src int_ba+0x48 r irq18 (i 2 c0) interrupt source identity 0xxxxx_xxxx irq19_src int_ba+0x4c r irq19 (i 2 c1) interrupt source identity 0xxxxx_xxxx irq20_src int_ba+0x50 r irq20 (can0) inte rrupt source identity 0xxxxx_xxxx irq21_src int_ba+0x54 r irq21 (reserved) in terrupt source identity 0xxxxx_xxxx irq22_src int_ba+0x58 r irq22 (reserved) in terrupt source identity 0xxxxx_xxxx numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 177 - revision v1.06 irq23_src int_ba+0x5c r irq23 (usbd) interrupt source identity 0xxxxx_xxxx irq24_src int_ba+0x60 r irq24 (ps2) interrupt source identity 0xxxxx_xxxx irq25_src int_ba+0x64 r irq25 (acmp) inte rrupt source identity 0xxxxx_xxxx irq26_src int_ba+0x68 r irq26 (pdma) inte rrupt source identity 0xxxxx_xxxx irq27_src int_ba+0x6c r irq27 (i2s) interrupt source identity 0xxxxx_xxxx irq28_src int_ba+0x70 r irq28 (pwrwu) interrupt source identity 0xxxxx_xxxx irq29_src int_ba+0x74 r irq29 (adc) interrupt source identity 0xxxxx_xxxx irq30_src int_ba+0x78 r irq30 (reserved) in terrupt source identity 0xxxxx_xxxx irq31_src int_ba+0x7c r irq31 (rtc) interrupt source identity 0xxxxx_xxxx nmi_sel int_ba+0x80 r/w nmi source interrupt select control register 0x0000_0000 mcu_irq int_ba+0x84 r/w mcu irq number identity register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 178 - revision v1.06 interrupt source identity register (irqn_src) register offset r/w description reset value irqn_src int_ba+0x00 ??.. int_ba+0x7c r irq0 (bod) interrupt source identity irq31 (rtc) interrupt source identity 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved int_src[3] int_src[2:0] bits address int-num descriptions [2:0] int_ba+0x00 0 bit2: 0 bit1: 0 bit0: bod_int [2:0] int_ba+0x04 1 bit2: 0 bit1: 0 bit0: wdt_int [2:0] int_ba+0x08 2 bit2: 0 bit1: 0 bit0: eint0 ? external interrupt 0 from pb.14 [2:0] int_ba+0x0c 3 bit2: 0 bit1: 0 bit0: eint1 ? external interrupt 1 from pb.15 [2:0] int_ba+0x10 4 bit2: 0 bit1: gpb_int bit0: gpa_int [2:0] int_ba+0x14 5 bit2: gpe_int bit1: gpd_int bit0: gpc_int [3:0] int_ba+0x18 6 bit3: pwm3_int bit2: pwm2_int bit1: pwm1_int numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 179 - revision v1.06 bit0: pwm0_int [3:0] int_ba+0x1c 7 bit3: pwm7_int bit2: pwm6_int bit1: pwm5_int bit0: pwm4_int [2:0] int_ba+0x20 8 bit2: 0 bit1: 0 bit0: tmr0_int [2:0] int_ba+0x24 9 bit2: 0 bit1: 0 bit0: tmr1_int [2:0] int_ba+0x28 10 bit2: 0 bit1: 0 bit0: tmr2_int [2:0] int_ba+0x2c 11 bit2: 0 bit1: 0 bit0: tmr3_int [2:0] int_ba+0x30 12 bit2: 0 bit1: 0 bit0: urt0_int [2:0] int_ba+0x34 13 bit2: 0 bit1: 0 bit0: urt1_int [2:0] int_ba+0x38 14 bit2: 0 bit1: 0 bit0: spi0_int [2:0] int_ba+0x3c 15 bit2: 0 bit1: 0 bit0: spi1_int [2:0] int_ba+0x40 16 bit2: 0 bit1: 0 bit0: spi2_int [2:0] int_ba+0x44 17 bit2: 0 bit1: 0 bit0: spi3_int [2:0] int_ba+0x48 18 bit2: 0 bit1: 0 bit0: i2c0_int [2:0] int_ba+0x4c 19 bit2: 0 bit1: 0 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 180 - revision v1.06 bit0: i 2 c1_int [2:0] int_ba+0x50 20 bit2: 0 bit1: 0 bit0: can0_int [2:0] int_ba+0x54 21 reserved [2:0] int_ba+0x58 22 reserved [2:0] int_ba+0x5c 23 bit2: 0 bit1: 0 bit0: usbd_int [2:0] int_ba+0x60 24 bit2: 0 bit1: 0 bit0: ps2_int [2:0] int_ba+0x64 25 bit2: 0 bit1: 0 bit0: acmp_int [2:0] int_ba+0x68 26 bit2: 0 bit1: 0 bit0: pdma_int [2:0] int_ba+0x6c 27 bit2: 0 bit1: 0 bit0: i2s_int [2:0] int_ba+0x70 28 bit2: 0 bit1: 0 bit0: pwrwu_int [2:0] int_ba+0x74 29 bit2: 0 bit1: 0 bit0: adc_int [2:0] int_ba+0x78 30 reserved [2:0] int_ba+0x7c 31 bit2: 0 bit1: 0 bit0: rtc_int nmi interrupt source select control regis ter (nmi_sel) register offset r/w description reset value nmi_sel int_ba+0x80 r/w nmi source interrupt select control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 181 - revision v1.06 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved nmi_sel[4:0] bits descriptions [31:5] reserved reserved [4:0] nmi_sel nmi interrupt source select the nmi interrupt to cortex-m0 can be selected from one of the peripheral interrupt by setting nmi_sel. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 182 - revision v1.06 mcu interrupt request source register (mcu_irq) register offset r/w description reset value mcu_irq int_ba+0x84 r/w mcu interrupt request source register 0x0000_0000 31 30 29 28 27 26 25 24 mcu_irq[31:24] 23 22 21 20 19 18 17 16 mcu_irq[23:16] 15 14 13 12 11 10 9 8 mcu_irq[15:8] 7 6 5 4 3 2 1 0 mcu_irq[7:0] bits descriptions [31:0] mcu_irq mcu irq source register the mcu_irq collects all the interrupts from the peripherals and generates the synchronous interrupt to cortex-m0. there are two modes to generate interrupt to cortex-m0, the normal mode and test mode. the mcu_irq collects all interrupts from each peripheral and synchronizes them then interrupts the cortex-m0. when the mcu_irq[n] is 0: set mcu_irq[n] 1 will generate an interrupt to cortex_m0 nvic[n]. when the mcu_irq[n] is 1 (mean an interrupt is assert), set 1 to the mcu_bit[n] will clear the interrupt and set mcu_irq[n] 0 : no any effect numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 183 - revision v1.06 5.2.8 system control register cortex-m0 status and operating mode control are managed system control registers. including cpuid, cortex-m0 interrupt priority and cortex-m0power manage ment can be controlled through these system control register for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?. r : read only, w : write only, r/w : both read and write register offset r/w description reset value scs_ba = 0xe000_e000 cpuid scs_ba+0xd00 r cpuid register 0x410c_c200 icsr scs_ba+0xd04 r/w interrupt control state register 0x0000_0000 aircr scs_ba+0xd0c r/w application interrupt and reset control register 0xfa05_0000 scr scs_ba+0xd10 r/w system control register 0x0000_0000 shpr2 scs_ba+0xd1c r/w system handler priority register 2 0x0000_0000 shpr3 scs_ba+0xd20 r/w system handler priority register 3 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 184 - revision v1.06 cpuid register (cpuid) register offset r/w description reset value cpuid scs_ba+0xd00 r cpuid register 0x410c_c200 31 30 29 28 27 26 25 24 implementer[7:0] 23 22 21 20 19 18 17 16 reserved part[3:0] 15 14 13 12 11 10 9 8 partno[11:4] 7 6 5 4 3 2 1 0 partno[3:0] revision[3:0] bits descriptions [31:24] implementer implementer code assigned by arm. ( arm = 0x41) [23:20] reserved reserved [19:16] part reads as 0xc for armv6-m parts [15:4] partno reads as 0xc20. [3:0] revision reads as 0x0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 185 - revision v1.06 interrupt control state register (icsr) register offset r/w description reset value icsr scs_ba+0xd04 r/w interrupt control state register 0x0000_0000 31 30 29 28 27 26 25 24 nmipendse t reserved pendsvset pendsvclr pendstset pendstclr reserved 23 22 21 20 19 18 17 16 isrpreemp t isrpending reserved vectpending[8:4] 15 14 13 12 11 10 9 8 vectpending[3:0] reserved vectactive [8] 7 6 5 4 3 2 1 0 vectactive[7:0] bits descriptions [31] nmipendset setting this bit will activate an nmi. since nmi is the highest priority exception, it will activate as soon as it is registered. reads back with current state (1 if pending, 0 if not). [30:29] reserved reserved [28] pendsvset set a pending pendsv interrupt. this is normally used to request a context switch. reads back with current state (1 if pending, 0 if not). [27] pendsvclr write 1 to clear a pending pendsv interrupt. this is a write only bit. [26] pendstset set a pending systick. reads back with current state (1 if pending, 0 if not). [25] pendstclr write 1 to clear a pending systick. this is a write only bit. [24] reserved reserved [23] isrpreempt if set, a pending exception will be serviced on exit from the debug halt state. this is a read only bit. [22] isrpending indicates if an external configurable (nvic generated) interrupt is pending. this is a read only bit. [21] reserved reserved [20:12] vectpending indicates the exception number for the hi ghest priority pending exception. the pending state includes the effect of memory-mapped enable and mask registers. it does not include the primask special-purpose register qualifier. a value of zero indicates no pending exceptions. this is a read only bit. [11:9] reserved reserved [8:0] vectactive 0 = thread mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 186 - revision v1.06 value > 1 = the exception number for the current executing exception. this is a read only bit. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 187 - revision v1.06 application interrupt and rese t co ntrol register (aircr) register offset r/w description reset value aircr scs_ba+0xd0c r/w application interrupt and reset control register 0xfa05_0000 31 30 29 28 27 26 25 24 vectorkey[15:8] 23 22 21 20 19 18 17 16 vectorkey[7:0] 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved sysresetr eq vectclkac tive reserved bits descriptions [31:16] vectorkey when write this register, this field should be 0x05fa, otherwise the write action will be unpredictable. [15:3] reserved reserved [2] sysresetreq writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested. the bit is a write only bit and self-clears as part of the reset sequence. [1] vectclractive set this bit to 1 will clears all active state information for fixed and configurable exceptions. the bit is a write only bit and can only be written when the core is halted. note: it is the debugger?s responsibility to re-initialize the stack. [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 188 - revision v1.06 system control register (scr) register offset r/w description reset value scr scs_ba+0xd10 r/w system control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved sevonpend reserved sleepdeep sleeponexi t reserved bits descriptions [31:5] reserved reserved [4] sevonpend when enabled, interrupt transitions from inac tive to pending are included in the list of wakeup events for the wfe instruction. [3] reserved reserved [2] sleepdeep a qualifying hint that indicates waking from sleep might take longer. [1] sleeponexit when set to 1, the core can enter a sleep state on an exception return to thread mode. this is the mode and exception level entered at reset, the base level of execution. [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 189 - revision v1.06 system handler priority register 2 (shpr2) register offset r/w description reset value shpr2 scs_ba+0xd1c r/w system handler priority register 2 0x0000_0000 31 30 29 28 27 26 25 24 pri_11 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bits descriptions [31:30] pri_11 priority of system handler 11 ? svcall ?0? denotes the highest priority and ?3? denotes lowest priority [29:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 190 - revision v1.06 system handler priority register 3 (shpr3) register offset r/w description reset value shpr3 scs_ba+0xd20 r/w system handler priority register 3 0x0000_0000 31 30 29 28 27 26 25 24 pri_15 reserved 23 22 21 20 19 18 17 16 pri_14 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bits descriptions [31:30] pri_15 priority of system handler 15 ? systick ?0? denotes the highest priority and ?3? denotes lowest priority [29:24] reserved reserved [23:22] pri_14 priority of system handler 14 ? pendsv ?0? denotes the highest priority and ?3? denotes lowest priority [21:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 191 - revision v1.06 5.3 clock controller 5.3.1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also im plements the power control function with the individually clock on/off control, clock source selection and a 4-bit clock divider. the chip will not enter power-down mode until cpu sets the power down enable bit (pwr_down_en) and cortex-m0 core executes the wfi instruction. after that, chip enter power-down mode and wait for wake-up interrupt source triggered to leave power-down mode. in the power down mode, the clock controller turns off the external 4~24 mhz crystal and internal 22.1184 mhz oscillator to reduce the overall system power consumption. 5.3.2 clock generator the clock generator consists of 5 clock sources which are listed below: z one external 32.768 khz crystal z one external 4~24 mhz crystal z one programmable pll fout(pll source consists of external 4~24 mhz crystal and internal 22.1184 mhz oscillator) z one internal 22.1184 mhz oscillator z one internal 10 khz oscillator xt_out external 4~24 mhz crystal xtl12m_en (pwrcon[0]) xt_in internal 22.1184 mhz oscillator osc22m_en (pwrcon[2]) 0 1 pll pll_src (pllcon[19]) pll fout x32o external 32.768 khz crystal 32.768 khz xtl32k_en (pwrcon[1]) x32i internal 10 khz oscillator osc10k_en(pwrcon[3]) 4~24 mhz 22.1184 mhz 10 khz figure 5-4 clock generator block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 192 - revision v1.06 5.3.3 system clock & systick clock the system clock has 5 clock sources which we re generated from clock generator block. the clock source switch depends on the register hclk_s (clksel0[2:0]). the block diagram is showed in figure 5-5. 1xx 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz hclk_s (clksel0[2:0]) 22.1184 mhz 000 1/(hclk_n+1) hclk_n (clkdiv[3:0]) cpu in power down mode cpu ahb apb cpuclk hclk pclk figure 5-5 system clock block diagram the clock source of systick in cortex-m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the sy stick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of t he register stclk_s (clksel0[5:3]. the block diagram is showed in figure 5-6. figure 5-6 systick clock control block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 193 - revision v1.06 5.3.4 peripherals clock the peripherals clock had different clock source switch setting which depends on the different peripheral. please refer the clksel1 and cl ksel2 register description in 5.3.7. 5.3.5 power down mode (deep sleep mode) clock when chip enters into power down mode, syst em clocks, some clock sources, and some peripheral clocks will be di sabled. some cloc k sources and peripherals clock are still active in power down mode. for theses clocks which still keep active list below: z clock generator ? internal 10 khz oscillator clock ? external 32.768 khz crystal clock z peripherals clock (when these ip adopt 32.768 khz or 10 khz as clock source) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 194 - revision v1.06 5.3.6 frequency divider output this device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power-of-2 divided clocks with the frequency from f in /2 1 to f in /2 16 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4-bit value in fsel (frqdiv[3:0]). when write 1 to divider_en (frq div[4]), the chained counter starts to count. when write 0 to divider_en (frqdiv[4]), the c hained counter continuously runs till divided clock reaches low state and stay in low state. figure 5-7 clock source of frequency divider 0000 0001 1110 1111 : : 16 to 1 mux 1/2 1/2 2 1/2 3 1/2 15 1/2 16 ... fsel (frqdiv[3:0]) clko frqdiv_clk 16 chained divide-by-2 counter divider_en (frqdiv[4]) enable divide-by-2 counter figure 5-8 block diagram of frequency divider numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 195 - revision v1.06 5.3.7 register map r: read only, w: write only, r/w: both read and write register offset r/w description reset value clk_ba = 0x5000_0200 pwrcon clk_ba+0x00 r/w system power down control register 0x0000_001x ahbclk clk_ba+0x04 r/w ahb devices clo ck enable control register 0x0000_000d apbclk clk_ba+0x08 r/w apb devices clock enable control register 0x0000_000x clkstatus clk_ba+0x0c r/w clock status monitor register (low density only) 0x0000_00xx clksel0 clk_ba+0x10 r/w clock source se lect control register 0 0x0000_003x clksel1 clk_ba+0x14 r/w clock source select control register 1 0xffff_ffff clksel2 clk_ba+0x1c r/w clock source select control register 2 0x0000_00f0 [1] 0x0000_00ff clkdiv clk_ba+0x18 r/w clock divider number register 0x0000_0000 pllcon clk_ba+0x20 r/w pll control register 0x0005_c22e frqdiv clk_ba+0x24 r/w frequency divider control register 0x0000_0000 note: [1] default value is 0x0000_00f0 in medium density; default value is 0x0000_00ff in low density numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 196 - revision v1.06 5.3.8 register description power down control register pwrcon except the bit[6], all the other bits are protect ed, program these bits nee d to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regi ster protection. reference the register regwrprot at address gcr_ba+0x100 register offset r/w description reset value pwrcon clk_ba+0x00 r/w system power down control register 0x0000_001x 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved pd_wait_cp u 7 6 5 4 3 2 1 0 pwr_down _en pd_wu_sts pd_wu_int_ en pd_wu_dly osc10k_en osc22m_en xtl32k_en xtl12m_en bits descriptions [31:9] reserved reserve [8] pd_wait_cpu this bit control the power down entry condition (write-protection bit) 1 = chip enter power down mode when the both pwr_down_en bit is set to 1 and cpu run wfi instruction. 0 = chip entry power down mode when the pwr_down_en bit is set to 1 [7] pwr_down_en system power down enable bit (write-protection bit) when cpu sets this bit to 1, the chip power down mode is enabled and chip power- down behavior will depends on the pd_wait_cpu bit (a) if the pd_wait_cpu is 0, then the chip enters power down mode immediately after the pwr_down_en bit set. (b) if the pd_wait_cpu is 1, then the chip keeps active till the cpu sleep mode is also active and then the chip enters power down mode when chip wakes up from power down mode, this bit is auto cleared. users need to set this bit again for next power down. when in power down mode, external 4~24 mhz crystal and the internal 22.1184 mhz oscillator will be disabled in this mode, but the external 32 khz crystal and internal 10 khz oscillator are not controlled by power down mode. when in power down mode, the pll and system clock are disabled, and ignored the clock source selection. the clocks of per ipheral are not controlled by power down mode, if the peripheral clock source is from external 32 khz crystal or the internal 10 khz oscillator. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 197 - revision v1.06 1 = chip enter the power down mode instant or wait cpu sleep command wfi 0 = chip operate in normal mode or cpu in idle mode (sleep mode) because of wfi command [6] pd_wu_sts power down mode wake up interrupt status set by ?power down wake up event?, it indicates that resume from power down mode? the flag is set if the gpio, usb, uart, wdt, can, acmp, bod or rtc wakeup occurred write 1 to clear the bit to zero. [5] pd_wu_int_en power down mode wake up interrupt enable (write-protection bit) 0 = disable 1 = enable the interrupt will occur when both pd_wu_sts and pd_wu_int_en are high. [4] pd_wu_dly enable the wake up delay counter (write-protection bit) when the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. the delayed clock cycle is 4096 clock cycles when chip work at external 4~24 mhz crystal, and 256 clock cycles when chip work at internal 22.1184 mhz oscillator. 1 = enable clock cycles delay 0 = disable clock cycles delay [3] osc10k_en internal 10 khz oscillator enable (write-protection bit) 1 = enable 10 khz oscillation 0 = disable 10 khz oscillation [2] osc22m_en internal 22.1184 mhz oscillator enable (write-protection bit) 1 = enable 22.1184 mhz oscillation 0 = disable 22.1184 mhz oscillation [1] xtl32k_en external 32.768 khz crystal enable (write-protection bit) 1 = enable external 32.768 khz crystal (normal operation) 0 = disable external 32.768 khz crystal [0] xtl12m_en external 4~24 mhz crystal enable (write-protection bit) the bit default value is set by flash contro ller user configuration register config0 [26:24]. when the default clock source is from external 4~24 mhz crystal, this bit is set to 1 automatically 1 = enable external 4~24 mhz crystal 0 = disable external 4~24 mhz crystal numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 198 - revision v1.06 register/instruction mode pwr_down_en pd_wait_cpu cpu run wfi instruction clock disable normal running mode 0 0 no all clock are disabled by control register idle mode (cpu entry sleep mode) 0 0 yes only cpu clock is disabled power_down mode 1 0 no most clocks are disabled except 10k/32k and some rtc/wdt/timer/pwm peripheral clock are still enabled. power_down mode (cpu entry deep sleep mode) 1 1 yes most clocks are disabled except 10k/32k and some rtc/wdt/timer/pwm peripheral clock are still enabled. table 5-5 power down mode control table when chip enter power down mode, user can wa keup chip by some interrupt sources. user should enable related interrupt sources and nvic irq enable bits (nvic_iser) before set pwr_down_en bit in pwrcon[7] to ensure chip can enter power down and be wakeup successfully. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 199 - revision v1.06 ahb devices clock enable control register ah bclk these bits for this register are used to enable/ disable clock for system clock pdma clock and ebi clock. register offset r/w description reset value ahbclk clk_ba+0x04 r/w ahb devices clo ck enable control register 0x0000_000d 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ebi_en isp_en pdma_en reserved bits descriptions [31:3] reserved reserved [3] ebi_en ebi controller clock enable control (low density only) 1 = enable the ebi engine clock 0 = disable the ebi engine clock [2] isp_en flash isp controller clock enable control 1 = enable the flash isp engine clock 0 = disable the flash isp engine clock [1] pdma_en pdma controller clock enable control 1 = enable the pdma engine clock 0 = disable the pdma engine clock [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 200 - revision v1.06 apb devices clock enable control register a pbclk these bits of this register are used to enable/ disable clock for peripheral controller clocks. register offset r/w description reset value apbclk clk_ba+0x08 r/w apb devices clock enable control register 0x0000_000x 31 30 29 28 27 26 25 24 ps2_en acmp_en i2s_en adc_en usbd_en reserved can0_en 23 22 21 20 19 18 17 16 pwm67_en pwm45_en pwm23_en pwm01_en reserved uart2_en uart1_en uart0_en 15 14 13 12 11 10 9 8 spi3_en spi2_en spi1_en spi0_en reserved i2c1_en i2c0_en 7 6 5 4 3 2 1 0 reserved fdiv_en tmr3_en tmr2_en tmr1_en tmr0_en rtc_en wdt_en bits descriptions [31] ps2_en ps2 clock enable 1 = enable ps2 clock 0 = disable ps2 clock [30] acmp_en analog comparator clock enable 1 = enable the analog comparator clock 0 = disable the analog comparator clock [29] i2s_en i2s clock enable 1 = enable i 2 s clock 0 = disable i 2 s clock [28] adc_en analog-digital-converter (adc) clock enable 1 = enable adc clock 0 = disable adc clock [27] usbd_en usb 2.0 fs device controller clock enable 1 = enable usb clock 0 = disable usb clock [26:25] reserved reserved [24] can0_en can bus controller-0 clock enable 1 = enable can0 clock 0 = disable can0 clock [23] pwm67_en pwm_67 clock enable (medium density only) 1 = enable pwm67 clock 0 = disable pwm67 clock numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 201 - revision v1.06 [22] pwm45_en pwm_45 clock enable (medium density only) 1 = enable pwm45 clock 0 = disable pwm45 clock [21] pwm23_en pwm_23 clock enable 1 = enable pwm23 clock 0 = disable pwm23 clock [20] pwm01_en pwm_01 clock enable 1 = enable pwm01 clock 0 = disable pwm01 clock [19] reserved reserved [18] uart2_en uart2 clock enable (medium density only) 1 = enable uart2 clock 0 = disable uart2 clock [17] uart1_en uart1 clock enable 1 = enable uart1 clock 0 = disable uart1 clock [16] uart0_en uart0 clock enable 1 = enable uart0 clock 0 = disable uart0 clock [15] spi3_en spi3 clock enable (medium density only) 1 = enable spi3 clock 0 = disable spi3 clock [14] spi2_en spi2 clock enable (medium density only) 1 = enable spi2 clock 0 = disable spi2 clock [13] spi1_en spi1 clock enable 1 = enable spi1 clock 0 = disable spi1 clock [12] spi0_en spi0 clock enable 1 = enable spi0 clock 0 = disable spi0 clock [11:10] reserved reserved [9] i2c1_en i 2 c1 clock enable 1 = enable i 2 c1 clock 0 = disable i 2 c1 clock [8] i2c0_en i 2 c0 clock enable 1 = enable i 2 c0 clock 0 = disable i 2 c0 clock [7] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 202 - revision v1.06 [6] fdiv_en frequency divider output clock enable 1 = enable fdiv clock 0 = disable fdiv clock [5] tmr3_en timer3 clock enable 1 = enable timer3 clock 0 = disable timer3 clock [4] tmr2_en timer2 clock enable 1 = enable timer2 clock 0 = disable timer2 clock [3] tmr1_en timer1 clock enable 1 = enable timer1 clock 0 = disable timer1 clock [2] tmr0_en timer0 clock enable 1 = enable timer0 clock 0 = disable timer0 clock [1] rtc_en real-time-clock apb interface clock enable this bit is used to control the rtc apb cl ock only, the rtc engine clock source is from the external 32.768 khz crystal. 1 = enable rtc clock 0 = disable rtc clock [0] wdt_en watchdog timer clock enable (write-protection bit) this bit is the protected bit. it means pr ogramming this needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. the bit default value is set by flash contro ller. user configuration register congig0 bit[31] 1 = enable watchdog timer clock 0 = disable watchdog timer clock numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 203 - revision v1.06 clock status register clks tatus these bits of this register are used to monitor if the chip clock source stable or not, and whether clock switch failed. (only support in low density) register offset r/w description reset value clkstatus clk_ba+0x0c r/w clock status monitor register 0x0000_00xx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 clk_sw_fai l reserved osc22m_st b osc10k_st b pll_stb xtl32k_stb xtl12m_stb bits descriptions [31:8] reserved reserved [7] clk_sw_fail clock switching fail flag (write-protection bit) 1 = clock switching failure 0 = clock switching success this bit is updated when software switches sy stem clock source. if switch target clock is stable, this bit will be set to 0. if switch target clock is not stable, this bit will be set to 1. write 1 to clear the bit to zero. [6:5] reserved reserved [4] osc22m_stb osc22m clock source stable flag 1 = osc22m clock is stable 0 = osc22m clock is not stable or disabled this is read only bit [3] osc10k_stb osc10k clock source stable flag 1 = osc10k clock is stable 0 = osc10k clock is not stable or disabled this is read only bit [2] pll_stb pll clock source stable flag 1 = pll clock is stable 0 = pll clock is not stable or disabled this is read only bit numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 204 - revision v1.06 [1] xtl32k_stb xtl32k clock source stable flag 1 = xtl32k clock is stable 0 = xtl32k clock is not stable or disabled this is read only bit [0] xtl12m_stb xtl12m clock source stable flag 1 = xtl12m clock is stable 0 = xtl12m clock is not stable or disabled this is read only bit numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 205 - revision v1.06 clock source select control register 0 clksel 0 register offset r/w description reset value clksel0 clk_ba+0x10 r/w clock source se lect control register 0 0x0000_003x 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved stclk_s hclk_s bits descriptions [31:6] reserved reserved [5:3] stclk_s cortex_m0 systick clock source select (write-protection bits) if syst_csr[2]=0, systick uses listed clock source below these bits are protected bit. it means progra mming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable regist er protection. reference the register regwrprot at address gcr_ba+0x100. 000 = clock source from exter nal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from exter nal 4~24 mhz crystal clock/2 011 = clock source from hclk/2 1xx = clock source from internal 22.1184 mhz oscillator clock/2 [2:0] hclk_s hclk clock source select (write-protection bits) 1. before clock switching, the relat ed clock sources (both pre-select and new- select) must be turn on 2. the 3-bit default value is reloaded from the value of cfosc ( config0 [26:24]) in user configuration register of flash c ontroller by any reset. therefore the default value is either 000b or 111b. 3. these bits are protected bit, it means pr ogramming this bit needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to dis able register protection. reference the register regwrprot at address gcr_ba+0x100. 000 = clock source from exte rnal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from pll clock 011 = clock source from inter nal 10 khz oscillator clock 1xx = clock source from internal 22.1184 mhz oscillator clock numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 206 - revision v1.06 clock source select control register 1 cl ksel1 before clock switching, the related clock source s (pre-select and new-select) must be turned on. register offset r/w description reset value clksel1 clk_ba+0x14 r/w clock source select control register 1 0xffff_ffff 31 30 29 28 27 26 25 24 pwm23_s pwm01_s can_s uart_s 23 22 21 20 19 18 17 16 reserved tmr3_s reserved tmr2_s 15 14 13 12 11 10 9 8 reserved tmr1_s reserved tmr0_s 7 6 5 4 3 2 1 0 reserved adc_s wdt_s bits descriptions [31:30] pwm23_s pwm2 and pwm3 clock source select pwm2 and pwm3 uses the same engine clo ck source, both of them use the same prescaler 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from external 32.768 khz crystal clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock [29:28] pwm01_s pwm0 and pwm1 clock source select pwm0 and pwm1 uses the same engine clo ck source, both of them use the same prescaler 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from external 32.768 khz crystal clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock [27:26] can_s can clock source select 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from pll clock 1x = clock source from internal 22.1184 mhz oscillator clock [25:24] uart_s uart clock source select 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from pll clock numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 207 - revision v1.06 1x = clock source from internal 22.1184 mhz oscillator clock [23] reserved reserved [22:20] tmr3_s timer3 clock source select 000 = clock source from exte rnal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from hclk 011 = clock source from external trigger 1xx = clock source from internal 22.1184 mhz oscillator clock [19] reserved reserved [18:16] tmr2_s timer2 clock source select 000 = clock source from exte rnal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from hclk 011 = clock source from external trigger 1xx = clock source from internal 22.1184 mhz oscillator clock [15] reserved reserved [14:12] tmr1_s timer1 clock source select 000 = clock source from exte rnal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from hclk 011 = clock source from external trigger 1xx = clock source from internal 22.1184 mhz oscillator clock [11] reserved reserved [10:8] tmr0_s timer0 clock source select 000 = clock source from exte rnal 4~24 mhz crystal clock 001 = clock source from exte rnal 32.768 khz crystal clock 010 = clock source from hclk 011 = clock source from external trigger 1xx = clock source from internal 22.1184 mhz oscillator clock [7:4] reserved reserved [3:2] adc_s adc clock source select 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from pll clock 1x = clock source from internal 22.1184 mhz oscillator clock [1:0] wdt_s watchdog timer clock source select (write-protection bits) these bits are protected bit, program this need to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable register protection. reference the register regwrprot at address gcr_ba+0x100. 00 = clock source from external 4~24 mhz crystal clock 01 = reserved 10 = clock source from hclk/2048 clock numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 208 - revision v1.06 11 = clock source from internal 10 khz oscillator clock numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 209 - revision v1.06 clock source select control register 2 clksel 2 before clock switching, the related clock source s (pre-select and new-select) must be turned on. register offset r/w description reset value clksel2 clk_ba+0x1c r/w clock source select control register 2 0x0000_00f0 [1] 0x0000_00ff note: [1] default value is 0x0000_00f0 in medium density; default value is 0x0000_00ff in low density 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 pwm67_s pwm45_s frqdiv_s i2s_s bits descriptions [31:8] reserved reserved [7:6] pwm67_s pwm6 and pwm7 clock source select (medium density only) pwm6 and pwm7 used the same engine clock source, both of them use the same prescaler 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from external 32.768 khz crystal clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock [5:4] pwm45_s pwm4 and pwm5 clock source select (medium density only) pwm4 and pwm5 used the same engine clock source, both of them use the same prescaler 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from external 32.768 khz crystal clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock [3:2] frqdiv_s clock divider clock source select 00 = clock source from external 4~24 mhz crystal clock 01 = clock source from external 32.768 khz crystal clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock [1:0] i2s_s i 2 s clock source select 00 = clock source from external 4~24 mhz crystal clock numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 210 - revision v1.06 01 = clock source from pll clock 10 = clock source from hclk 11 = clock source from internal 22.1184 mhz oscillator clock numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 211 - revision v1.06 clock divider register (clkdiv) register offset r/w description reset value clkdiv clk_ba+0x18 r/w clock divider number register 0x0000_0000 31 30 29 28 27 26 25 24 reserved can_n_h 23 22 21 20 19 18 17 16 adc_n 15 14 13 12 11 10 9 8 can_n_l uart_n 7 6 5 4 3 2 1 0 usb_n hclk_n bits descriptions [31:30] reserved reserved [29:24] can_n_h can clock divide number from can clock source (low density only) the can clock frequency = (can clock source frequency ) / (can_n + 1) which can_n = 16 * can_n_h + can_n_l [23:16] adc_n adc clock divide number from adc clock source the adc clock frequency = (adc clock source frequency ) / (adc_n + 1) [15:12] can_n_l can clock divide number from can clock source the can clock frequency = (can clock source frequency ) / (can_n + 1) which can_n = 16 * can_n_h + can_n_l [11:8] uart_n uart clock divide number from uart clock source the uart clock frequency = (uart clock source frequency ) / (uart_n + 1) [7:4] usb_n usb clock divide number from pll clock the usb clock frequency = (pll frequency ) / (usb_n + 1) [3:0] hclk_n hclk clock divide number from hclk clock source the hclk clock frequency = (hclk clock source frequency) / (hclk_n + 1) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 212 - revision v1.06 pll control register p llcon the pll reference clock input is from the exte rnal 4~24 mhz crystal clock input or from the internal 22.1184 mhz oscillator. these registers are use to control the pll output frequency and pll operating mode register offset r/w description reset value pllcon clk_ba+0x20 r/w pll control register 0x0005_c22e 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pll_src oe bp pd 15 14 13 12 11 10 9 8 out_dv in_dv fb_dv 7 6 5 4 3 2 1 0 fb_dv bits descriptions [31:20] reserved reserved [19] pll_src pll source clock select 1 = pll source clock from internal 22.1184 mhz oscillator 0 = pll source clock from external 4~24 mhz crystal [18] oe pll oe (fout enable) pin control 0 = pll fout enable 1 = pll fout is fixed low [17] bp pll bypass control 0 = pll is in normal mode (default) 1 = pll clock output is same as clock input (xtalin) [16] pd power down mode if set the pwr_down_en bit to 1 in pwrc on register, the pll will enter power down mode too. 0 = pll is in normal mode 1 = pll is in power-down mode (default) [15:14] out_dv pll output divider control pins refer to the formulas below the table. [13:9] in_dv pll input divider control pins refer to the formulas below the table. [8:0] fb_dv pll feedback divider control pins refer to the formulas below the table. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 213 - revision v1.06 output clock frequency setting nonr nf fin fout 1 = constrain: 1. mhz finmhz 150 2.3 << 2. mhz nr fin khz 8 *2 800 << 3. preferred is fco mhz mhz nr nf fin fco mhz < <=< 120 200 100 symbol description fout output clock frequency fin input (reference) clock frequency nr input divider (in_dv + 2) nf feedback divider (fb_dv + 2) no out_dv = ?00? : no = 1 out_dv = ?01? : no = 2 out_dv = ?10? : no = 2 out_dv = ?11? : no = 4 default frequency setting the default value : 0xc22e fin = 12 mhz nr = (1+2) = 3 nf = (46+2) = 48 no = 4 fout = 12/4 x 48 x 1/3 = 48mhz numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 214 - revision v1.06 frequency divider control register (frqdiv) register offset r/w description reset value frqdiv clk_ba+ 24 r/w frequency divider control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved divider_en fsel bits descriptions [31:5] reserved reserved [4] divider_en frequency divider enable bit 0 = disable frequency divider 1 = enable frequency divider [3:0] fsel divider output frequency selection bits the formula of output frequency is f out = f in /2 (n+1) f in is the input clock frequency. f out is the frequency of divider output clock. n is the 4-bit value of fsel[3:0]. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 215 - revision v1.06 5.4 usb device controller (usb) 5.4.1 overview there is one set of usb 2.0 full-speed device controller and transceiver in this device. it is compliant with usb 2.0 full-speed device specification and support control/bulk/interrupt/ isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, t he cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. users need to set the effective starting address of sram for each endpoint buffer through ?buffer segmentation register (bufsegx)?. this device controller contains 6 configurable endpoints. each endpoint can be configured as in, out, or setup packet type. the function add ress of the device and endpoint number in each endpoint shall be configured properly in advance for receive or transmit a data packet. the transmit/receive length in each endpoint is defined in maximum payload register (mxpldx) and the handshakes between host and device are handled in it. there are four different interrupt events in this controller. they are the wake up function, device plug-in or plug-out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrup t, and users just need to check the related event flags in interrupt event status register (usb_ intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint. a software-disable function is also support for th is usb controller. it is used to simulate the disconnection of this device from the host. if user enables drvse0 bit (usb_drvse0), the usb controller will force the output of usb_dp and usb_dm to level low and its function is disabled. after disable the drvse0 bit, host wi ll enumerate the usb device again. reference: universal serial bus specification revision 1.1 5.4.2 features this universal serial bus (usb) performs a seri al interface with a single connector type for attaching all usb peripherals to the host system. following is the feature listing of this usb. z compliant with usb 2.0 full-speed specification z provide 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) z support control/bulk/interr upt/isochronous transfer type z support suspend function when no bus activity existing for 3 ms z provide 6 endpoints for confi gurable control/bulk/interrup t/isochronous tr ansfer types and maximum 512 bytes buffer size z provide remote wakeup capability numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 216 - revision v1.06 5.4.3 block diagram figure 5-9 usb block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 217 - revision v1.06 5.4.4 function description 5.4.4.1 sie (serial interface engine) the sie is the front-end o f the device controller and handles most of the usb packet protocol. the sie typically comprehends signaling up to the transaction level. the functions that it handles could include: z packet recognition, transaction sequencing z sop, eop, reset, resume signal detection/generation z clock/data separation z nrzi data encoding/decoding and bit-stuffing z crc generation and checking (for token and data) z packet id (pid) generation and checking/ decoding z serial-parallel/ parallel-serial conversion 5.4.4.2 endpoint control there are 6 e ndpoints in this controller. each of the endpoint can be configured as control, bulk, interrupt, or isochronous transfer type. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. it is also used to manage the data sequential synchronization, endpoint state co ntrol, current endpoint start addre ss, current transaction status, and data buffer status in each endpoint. 5.4.4.3 digital phase lock loop the bit rate of usb data is 12 mhz. the dp ll u se the 48 mhz which comes from the clock controller to lock the input data rxdp and rxdm. the 12 mhz bit rate clock is also converted from dpll. 5.4.4.4 floating de-bounce a usb device may be plu g-in or plug-out from t he usb host. in order to monitor the state of a usb device when it is detached from the usb hos t, the device controller provides hardware de- bounce for usb floating detect interrupt to av oid bounce problems on usb plug-in or unplug. floating detect interrupt appears about 10 ms later than usb plug-in or plug-out. a user can acknowledge usb plug-in/plug-out by reading register ?usb_fldet?. the flag in ?fldet? represents the current state on the bus withou t de-bounce. if the fldet is 1, it means the controller has plug-in the usb. if the user polli ng this flag to check usb state, he/she must add software de-bounce if necessary. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 218 - revision v1.06 5.4.4.5 interrupt this usb provides 1 interrupt vector with 4 interrupt events (wakeup, fldet, usb and bus). the wakeup event is used to wake up the syst em clock when the power down mode is enabled. (the power mode function is defined in system power down control register, pwrcon). the fldet event is used for usb plug-in or unplug . the usb event notifies users of some usb requests, like in ack, out ack etc., and the bus event notifies users of some bus events, like suspend, resume, etc. user must set related bits in the interrupt enable register (usb_inten) of usb device controller to enable usb interrupts. wakeup interrupt is only present when the chip entered power down mode and then wakeup event had happened. after the chip enters powe r down mode, any change on usb_dp, usb_dm and floating detect pin can wake up this chip (provided that usb wakeup function is enabled). if this change is not intentionally, for example, a noise on floating detect pin, no interrupt but wakeup interrupt will occur. after usb wakeup, this interrupt will occur when no other usb interrupt events are present for more than 20ms. t he following figure is the control flow of wakeup interrupt. figure 5-10 wakeup interrupt operation flow usb interrupt is used to notify users of any usb event on the bus, and a user can read epsts (usb_epsts[25:8]) and epevt5~0 (usb_intsts[21:16]) to know what kind of request is to which endpoint and take necessary responses. same as usb interrupt, bus interrupt notifies users of some bus events, like usb reset, suspend, time-out, and resume. a user can read usb_attr to acknowledge bus events. 5.4.4.6 power saving usb turns of f phy transceiver automatically to save power while this chip enters power down numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 219 - revision v1.06 mode. furthermore, a user can write 0 into usb_attr[4] to turn off phy under special circumstances like suspend to save power. 5.4.4.7 buffer control there is 512 bytes sram in the controller and the 6 endpoints share this buffer. the user shall configure each endpoint?s effective starting address in the buffer segmentation register before the usb function active. the buffer control block is used to control each endpoint?s effective starting address and its sram size is defined in the mxpld register. figure 5-11 depicts the starting address for each en dpoint according the content of bufseg and mxpld registers. if the bufseg0 is programmed as 0x08h and mxpld0 is set as 0x40h, the sram size of endpoint 0 is start from usb_ba + 0x108h and end in usb_ba + 0x148h. (note: the usb sram base is usb_ba + 0x100h). setup token buffer: 8 bytes ep0 sram buffer: 64 bytes ep1 sram buffer: 64 bytes ep2 sram buffer ep3 sram buffer usb sram start address ep0 sa = usb_ba + 0x0108h mxpld0 = 0x40 usb sram = usb_ba + 0x0100h ep1 sa = usb_ba + 0x0148h mxpld1 = 0x40 ep2 sa = usb_ba + 0x0188h ep3 sa = usb_ba + 0x0200h 512 bytes bufseg0 = 0x008 bufseg1 = 0x048 bufseg2 = 0x088 bufseg3 = 0x100 figure 5-11 endpoint sram structure numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 220 - revision v1.06 5.4.4.8 handling transactions with usb device peripheral user can use interrupt or polling usb_intsts to monitor the usb transactions, when transactions occur, usb_intsts will be set by hardware and send an interrupt request to cpu (if related interrupt enabled), or user can polling u sb_intsts to get these events without interrupt. the following is the control flow with interrupt enable. when usb host has requested data from device controller, users need to prepare related data into the specified endpoint buffer in advance. afte r buffering the required data, users need to write the actual data length in the specified maxpld register. once this regi ster is written, the internal signal ?in_rdy? will be asserted and the buffering data will be transmitted immediately after receiving associated in token from host. note that after transferring the specified data, the signal ?in_rdy? will de-assert autom atically by hardware. figure 5-12 setup transaction followed by data in transaction alternatively, when usb host wants to transmit data to the out endpoint in the device controller, hardware will buffer these data to the specifie d endpoint buffer. after this transaction is completed, hardware will record the data length in related maxpld register and de-assert the signal ?out_rdy?. this will av oid hardware accepting next transaction until users move out current data in the related endpoint buffer. once users have processed this transaction, the related register ?maxpld? needs to be written by firmware to assert the signal ?out_rdy? again to accept next transaction. figure 5-13 data out transfer numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 221 - revision v1.06 5.4.5 register and memory map r : read only, w : write only, r/w : both read and write register offset r/w description reset value usb_ba = 0x4006_0000 usb_inten usb_ba+0x000 r/w usb interrupt enable register 0x0000_0000 usb_intsts usb_ba+0x004 r/w usb interrupt event status register 0x0000_0000 usb_faddr usb_ba+0x008 r/w usb device fu nction address register 0x0000_0000 usb_epsts usb_ba+0x00c r usb endpoint status register 0x0000_00x0 usb_attr usb_ba+0x010 r/w usb bus status and attribution register 0x0000_0040 usb_fldet usb_ba+0x014 r usb floating detected register 0x0000_0000 usb_bufseg usb_ba+0x018 r/w setup token buffer segmentation register 0x0000_0000 usb_bufseg0 usb_ba+0x020 r/w endpoint 0 buffer segmentation register 0x0000_0000 usb_mxpld0 usb_ba+0x024 r/w endpoint 0 maximal payload register 0x0000_0000 usb_cfg0 usb_ba+0x028 r/w endpoint 0 configuration register 0x0000_0000 usb_cfgp0 usb_ba+0x02c r/w endpoint 0 set stall and clear in/out ready control register 0x0000_0000 usb_bufseg1 usb_ba+0x030 r/w endpoint 1 buffer segmentation register 0x0000_0000 usb_mxpld1 usb_ba+0x034 r/w endpoint 1 maximal payload register 0x0000_0000 usb_cfg1 usb_ba+0x038 r/w endpoint 1 configuration register 0x0000_0000 usb_cfgp1 usb_ba+0x03c r/w endpoint 1 set stall and clear in/out ready control register 0x0000_0000 usb_bufseg2 usb_ba+0x040 r/w endpoint 2 buffer segmentation register 0x0000_0000 usb_mxpld2 usb_ba+0x044 r/w endpoint 2 maximal payload register 0x0000_0000 usb_cfg2 usb_ba+0x048 r/w endpoint 2 configuration register 0x0000_0000 usb_cfgp2 usb_ba+0x04c r/w endpoint 2 set stall and clear in/out ready control register 0x0000_0000 usb_bufseg3 usb_ba+0x050 r/w endpoint 3 buffer segmentation register 0x0000_0000 usb_mxpld3 usb_ba+0x054 r/w endpoint 3 maximal payload register 0x0000_0000 usb_cfg3 usb_ba+0x058 r/w endpoint 3 configuration register 0x0000_0000 usb_cfgp3 usb_ba+0x05c r/w endpoint 3 set stall and clear in/out ready control register 0x0000_0000 usb_bufseg4 usb_ba+0x060 r/w endpoint 4 buffer segmentation register 0x0000_0000 usb_mxpld4 usb_ba+0x064 r/w endpoint 4 maximal payload register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 222 - revision v1.06 usb_cfg4 usb_ba+0x068 r/w endpoint 4 configuration register 0x0000_0000 usb_cfgp4 usb_ba+0x06c r/w endpoint 4 set stall and clear in/out ready control register 0x0000_0000 usb_bufseg5 usb_ba+0x070 r/w endpoint 5 buffer segmentation register 0x0000_0000 usb_mxpld5 usb_ba+0x074 r/w endpoint 5 maximal payload register 0x0000_0000 usb_cfg5 usb_ba+0x078 r/w endpoint 5 configuration register 0x0000_0000 usb_cfgp5 usb_ba+0x07c r/w endpoint 5 set stall and clear in/out ready control register 0x0000_0000 usb_drvse0 usb_ba+0x090 r/w usb drive se0 control register 0x0000_0001 memory type address size description usb_ba = 0x4006_0000 sram usb_ba+0x100 ~ usb_ba+0x2ff 512 bytes the sram is used for the entire endpoints buffer. refer to section 5.4.4.7 for the endpoint sram structure and its description. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 223 - revision v1.06 5.4.6 register description usb interrupt enable register (usb_inten) register offset r/w description reset value usb_inten usb_ba+0x000 r/w usb interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 innak_en reserved wakeup_en 7 6 5 4 3 2 1 0 reserved wakeup_ie fldet_ie usb_ie bus_ie bits descriptions [31:16] reserved reserved [15] innak_en active nak function and its status in in token 1 = the nak status is updated into the endpoint status register, usb_epsts, when it is set to 1 and there is nak response in in token. it also enable the interrupt event when the device responds nak after receiving in token 0 = the nak status doesn?t be updated into the endpoint status register when it was set to 0. it also disable the interrupt event when device responds nak after receiving in token [14:9] reserved reserved [8] wakeup_en wake up function enable 1 = enable usb wakeup function 0 = disable usb wakeup function [7:4] reserved reserved [3] wakeup_ie usb wake up interrupt enable 1 = enable wakeup interrupt 0 = disable wakeup interrupt [2] fldet_ie floating detected interrupt enable 1 = enable floating detect interrupt 0 = disable floating detect interrupt [1] usb_ie usb event interrupt enable 1 = enable usb event interrupt 0 = disable usb event interrupt numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 224 - revision v1.06 [0] bus_ie bus event interrupt enable 1 = enable bus event interrupt 0 = disable bus event interrupt numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 225 - revision v1.06 usb interrupt event status register (usb_intsts) this register is usb interrupt event status r egister; clear by read usb_epsts, usb_attr or usb_fldet or by write ?1? to the corresponding bit. register offset r/w description reset value usb_intsts usb_ba+0x004 r/w usb interrupt event status register 0x0000_0000 31 30 29 28 27 26 25 24 setup reserved 23 22 21 20 19 18 17 16 reserved epevt5 epevt4 epevt3 epevt2 epevt1 epevt0 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved wakeup_st s fldet_sts usb_sts bus_sts bits descriptions [31] setup setup event status 1 = setup event occurred, cleared by write 1 to usb_intsts[31] 0 = no setup event [30:22] reserved reserved [21] epevt5 endpoint 5?s usb event status 1 = usb event occurred on endpoint 5, check usb_epsts[25:23] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[21] or usb_intsts[1] 0 = no event occurred in endpoint 5 [20] epevt4 endpoint 4?s usb event status 1 = usb event occurred on endpoint 4, check usb_epsts[22:20] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[20] or usb_intsts[1] 0 = no event occurred in endpoint 4 [19] epevt3 endpoint 3?s usb event status 1 = usb event occurred on endpoint 3, check usb_epsts[19:17] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[19] or usb_intsts[1] 0 = no event occurred in endpoint 3 [18] epevt2 endpoint 2?s usb event status 1 = usb event occurred on endpoint 2, check usb_epsts[16:14] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[18] or usb_intsts[1] 0 = no event occurred in endpoint 2 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 226 - revision v1.06 [17] epevt1 endpoint 1?s usb event status 1 = usb event occurred on endpoint 1, check usb_epsts[13:11] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[17] or usb_intsts[1] 0 = no event occurred in endpoint 1 [16] epevt0 endpoint 0?s usb event status 1 = usb event occurred on endpoint 0, check usb_epsts[10:8] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[16] or usb_intsts[1] 0 = no event occurred in endpoint 0 [15:4] reserved reserved [3] wakeup_sts wakeup interrupt status 1 = wakeup event occurred, cleared by write 1 to usb_intsts[3] 0 = no wakeup event is occurred [2] fldet_sts floating detected interrupt status 1 = there is attached/detached event in the usb bus and it is cleared by write 1 to usb_intsts[2]. 0 = there is not attached/detached event in the usb [1] usb_sts usb event interrupt status the usb event includes the setup token, in token, out ack, iso in, or iso out events in the bus. 1 = usb event occurred, check epsts0~5[2:0] to know which kind of usb event was occurred, cleared by write 1 to usb_intsts[1] or epsts0~5 and setup (usb_intsts[31]) 0 = no any usb event is occurred [0] bus_sts bus interrupt status the bus event means that there is one of the suspense or the resume function in the bus. 1 = bus event occurred; check usb_attr[3:0] to know which kind of bus event was occurred, cleared by write 1 to usb_intsts[0]. 0 = no any bus event is occurred numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 227 - revision v1.06 usb device function address register (usb_faddr) a seven-bit value uses as the address of a device on the usb bus. register offset r/w description reset value usb_faddr usb_ba+0x008 r/w usb device fu nction address register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved faddr bits descriptions [31:7] reserved reserved [6:0] faddr usb device?s function address numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 228 - revision v1.06 usb endpoint status re gister (usb_epsts) register offset r/w description reset value usb_epsts usb_ba+0x00c r usb endpoint status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved epsts5[2:1] 23 22 21 20 19 18 17 16 epsts5[0] epsts4[2:0] epsts3[2:0] epsts2[2] 15 14 13 12 11 10 9 8 epsts2[1:0] epsts1[2:0] epsts0[2:0] 7 6 5 4 3 2 1 0 overrun reserved bits descriptions [31:26] reserved reserved [25:23] epsts5 endpoint 5 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack 111 = isochronous transfer end [22:20] epsts4 endpoint 4 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack 111 = isochronous transfer end [19:17] epsts3 endpoint 3 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 229 - revision v1.06 111 = isochronous transfer end [16:14] epsts2 endpoint 2 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack 111 = isochronous transfer end [13:11] epsts1 endpoint 1 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack 111 = isochronous transfer end [10:8] epsts0 endpoint 0 bus status these bits are used to indicate th e current status of this endpoint 000 = in ack 001 = in nak 010 = out packet data0 ack 110 = out packet data1 ack 011 = setup ack 111 = isochronous transfer end [7] overrun overrun it indicates that the received data is over the maximum payload number or not. 1 = it indicates that the out data more than the max payload in mxpld register or the setup data more than 8 bytes 0 = no overrun [6:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 230 - revision v1.06 usb bus status and attribution register (usb_attr) register offset r/w description reset value usb_attr usb_ba+0x010 r/w usb bus status and attribution register 0x0000_0040 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved bytem pwrdn dppu_en 7 6 5 4 3 2 1 0 usb_en reserved rwakeup phy_en timeout resume suspend usbrst bits descriptions [31:11] reserved reserved [10] bytem cpu access usb sram size mode select 1 = byte mode: the size of the transfer from cpu to usb sram can be byte only. 0 = word mode: the size of the transfer from cpu to usb sram can be word only. [9] pwrdn power down phy transceiver, low active 1 = turn-on related circuit of phy transceiver 0 = power-down related circuit of phy transceiver [8] dppu_en pull-up resistor on usb_dp enable 1 = the pull-up resistor in usb_dp bus active 0 = disable the pull-up resistor in usb_dp bus [7] usb_en usb controller enable 1 = enable usb controller 0 = disable usb controller [6] reserved reserved [5] rwakeup remote wake up 1 = force usb bus to k (usb_dp low, usb_dm: high) state, used for remote wake- up 0 = release the usb bus from k state [4] phy_en phy transceiver function enable 1 = enable phy transceiver function 0 = disable phy transceiver function [3] timeout time out status 1 = bus no any response more than 18 bits time numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 231 - revision v1.06 0 = no time out it is a read only bit. [2] resume resume status 1 = resume from suspend 0 = no bus resume it is a read only bit. [1] suspend suspend status 1 = bus idle more than 3ms, either cable is plugged off or host is sleeping 0 = bus no suspend it is a read only bit. [0] usbrst usb reset status 1 = bus reset when se0 (single-ended 0) more than 2.5us 0 = bus no reset it is a read only bit. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 232 - revision v1.06 floating detection register (usb_fldet) register offset r/w description reset value usb_fldet usb_ba+0x014 r usb floating detected register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved fldet bits descriptions [31:1] reserved reserved [0] fldet device floating detected 1 = when the controller is attached into the bus, this bit will be set as 1 0 = the controller didn?t attached into the usb host numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 233 - revision v1.06 buffer segmentation register (usb_bufseg) for setup token only. register offset r/w description reset value usb_bufseg usb_ba+0x018 r/w setup token buffer segmentation register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved bufseg[8] 7 6 5 4 3 2 1 0 bufseg[7:3] reserved bits descriptions [31:9] reserved reserved [8:3] bufseg it is used to indicate the offset address for the setup token with the usb sram starting address. the effective starting address is usb_sram address + { bufseg[8:3], 3?b000} where the usb_sram address = usb_ba + 0x100h. note: it is used for setup token only. [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 234 - revision v1.06 buffer segmentation register (bufsegx) x = 0~5 register offset r/w description reset value usb_bufseg0 usb_ba+0x020 r/w endpoint 0 buffer segmentation register 0x0000_0000 usb_bufseg1 usb_ba+0x030 r/w endpoint 1 buffer segmentation register 0x0000_0000 usb_bufseg2 usb_ba+0x040 r/w endpoint 2 buffer segmentation register 0x0000_0000 usb_bufseg3 usb_ba+0x050 r/w endpoint 3 buffer segmentation register 0x0000_0000 usb_bufseg4 usb_ba+0x060 r/w endpoint 4 buffer segmentation register 0x0000_0000 usb_bufseg5 usb_ba+0x070 r/w endpoint 5 buffer segmentation register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved bufseg[8]x 7 6 5 4 3 2 1 0 bufseg[7:3]x reserved bits descriptions [31:9] reserved reserved [8:3] bufsegx it is used to indicate the offset address for each endpoint with the usb sram starting address. the effective starting address of the endpoint is usb_sram address + { bufseg[8:3], 3?b000} where the usb_sram address = usb_ba + 0x100h. refer to section 5.4.4.7 for the endpoint sram structure and its description. [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 235 - revision v1.06 maximal payload register (usb_mxpldx) x = 0~5 register offset r/w description reset value usb_mxpld0 usb_ba+0x024 r/w endpoint 0 maximal payload register 0x0000_0000 usb mxpld1 usb_ba+0x034 r/w endpoint 1 maximal payload register 0x0000_0000 usb mxpld2 usb_ba+0x044 r/w endpoint 2 maximal payload register 0x0000_0000 usb mxpld3 usb_ba+0x054 r/w endpoint 3 maximal payload register 0x0000_0000 usb mxpld4 usb_ba+0x064 r/w endpoint 4 maximal payload register 0x0000_0000 usb mxpld5 usb_ba+0x074 r/w endpoint 5 maximal payload register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved mxpld[8] 7 6 5 4 3 2 1 0 mxpld[7:0] bits descriptions [31:9] reserved reserved [8:0] mxpld maximal payload it is used to define the data length which is tr ansmitted to host (in token) or the actual data length which is received from the host (out token). it also used to indicate that the endpoint is ready to be transmitted in in token or received in out token. (1). when the register is written by cpu, for in token, the value of mxpld is us ed to define the data length to be transmitted and indicate the data buffer is ready. for out token, it means that the controller is ready to receive data from the host and the value of mxpld is the maximal data length comes from host. (2). when the register is read by cpu, for in token, the value of mxpld is i ndicated the data length be transmitted to host for out token, the value of mxpld is indi cated the actual data length receiving from host. note that once mxpld is written, the data packets will be transmitted/received immediately after in/out token arrived. configuration register (usb_cfgx) x = 0~5 register offset r/w description reset value numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 236 - revision v1.06 usb_cfg0 usb_ba+0x028 r/w endpoint 0?s c onfiguration register 0x0000_0000 usb cfg1 usb_ba+0x038 r/w endpoint 1?s c onfiguration register 0x0000_0000 usb cfg2 usb_ba+0x048 r/w endpoint 2?s c onfiguration register 0x0000_0000 usb cfg3 usb_ba+0x058 r/w endpoint 3?s c onfiguration register 0x0000_0000 usb cfg4 usb_ba+0x068 r/w endpoint 4?s c onfiguration register 0x0000_0000 usb cfg5 usb_ba+0x078 r/w endpoint 5?s c onfiguration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved cstall reserved 7 6 5 4 3 2 1 0 dsq_sync state isoch ep_num bits descriptions [31:10] reserved reserved [9] cstall clear stall response 1 = clear the device to response stall handshake in setup stage 0 = disable the device to clear the stall handshake in setup stage [8] reserved reserved [7] dsq_sync data sequence synchronization 1 = data1 pid 0 = data0 pid it is used to specify the data0 or data1 pi d in the following in token transaction. h/w will toggle automatically in in token base on the bit. [6:5] state endpoint state 00 = endpoint is disabled 01 = out endpoint 10 = in endpoint 11 = undefined [4] isoch isochronous endpoint this bit is used to set the endpoint as isochronous endpoi nt, no handshake. 1 = isochronous endpoint 0 = no isochronous endpoint numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 237 - revision v1.06 [3:0] ep_num endpoint number these bits are used to define the endpoint number of the current endpoint numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 238 - revision v1.06 extra configuration register (usb_cfgpx) x = 0~5 register offset r/w description reset value usb_cfgp0 usb_ba+0x02c r/w endpoint 0 set stall and clear in/out ready control register 0x0000_0000 usb_cfgp1 usb_ba+0x03c r/w endpoint 1 set stall and clear in/out ready control register 0x0000_0000 usb_cfgp2 usb_ba+0x04c r/w endpoint 2 set stall and clear in/out ready control register 0x0000_0000 usb_cfgp3 usb_ba+0x05c r/w endpoint 3 set stall and clear in/out ready control register 0x0000_0000 usb_cfgp4 usb_ba+0x06c r/w endpoint 4 set stall and clear in/out ready control register 0x0000_0000 usb_cfgp5 usb_ba+0x07c r/w endpoint 5 set stall and clear in/out ready control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved sstall clrrdy bits descriptions [31:2] reserved reserved [1] sstall set stall 1 = set the device to respond stall automatically 0 = disable the device to response stall [0] clrrdy clear ready when the mxpld register is set by user, it means that the endpoint is ready to transmit or receive data. if the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0. for in token, write ?1? is used to clear the in token had ready to transmit the data to usb. for out token, write ?1? is used to clear the out token had ready to receive the data from usb. this bit is write 1 only and it is always 0 when it was read back. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 239 - revision v1.06 usb drive se0 register (usb_drvse0) register offset r/w description reset value usb_drvse0 usb_ba+0x090 r/w force usb phy to drive se0 0x0000_0001 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved drvse0 bits descriptions [31:1] reserved reserved [0] drvse0 drive single ended zero in usb bus the single ended zero (se0) is when bot h lines (usb_dp and usb_dm) are being pulled low. 1 = force usb phy transceiver to drive se0 0 = none numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 240 - revision v1.06 5.5 general purpose i/o 5.5.1 overview numicro ? nuc100 series medium density has up to 80 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 80 pins are arranged in 5 ports named with gpioa, gpiob, gpioc, gpiod and gpioe. each port equips maximum 16 pins. each one of the 80 pins is independent and has the corresponding register bits to control the pin mode function and data. numicro ? nuc100 series low density has up to 65 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration and package. these 65 pins are arranged in 4 ports named with gpioa, gpiob, gpioc and gpiod with each port equips maximum 16 pins and another port named gpioe with 1 pins pe.5. the i/o type of each of i/o pins can be configur ed by software individually as input, output, open- drain or quasi-bidirectional mode. after reset, the i/o type of all pins stay in quasi-bidirectional mode and port data register gpiox_dout[15:0] resets to 0x0000_ffff. each i/o pin equips a very weakly individual pull-up resistor which is about 110k ~300k for v dd is from 5.0v to 2.5v. 5.5.2 features z four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence z ttl/schmitt trigger input selectable z i/o pin can be configured as interrupt source with edge/level setting z high driver and high sink io mode support numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 241 - revision v1.06 5.5.3 function description 5.5.3.1 input mode explanation set gpiox_pmd (pm dn[1:0]) to 00b the gpiox port [n] pin is in input mode and the i/o pin is in tri-state (high impedance) without output drive capabi lity. the gpiox_pin value reflects the status of the corresponding port pins. 5.5.3.2 output mode explanation set gpiox_pmd (pm dn[1:0]) to 01b the gpiox port [n] pin is in output mode and the i/o pin supports digital output function with source/sink current capability. the bit value in the corresponding bit [n] of gpiox_dout is driven on the pin. port pin input data port latch data p n vdd figure 5-14 push-pull output numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 242 - revision v1.06 5.5.3.3 open-drain mode explanation set gpiox_pmd (pmdn[1:0]) to 10b the gpiox port [n] pin is in open-drain mo de and the digital output function of i/o pin supports only sink cu rrent capability, an additional pull-up register is needed for driving high state. if the bit value in the corresponding bit [n] of gpiox_dout is 0, the pin drive a ?low? output on the pin. if the bit val ue in the corresponding bit [n] of gpiox_dout is 1, the pin output drives high that is controlled by external pull high resistor. port pin port latch data n input data figure 5-15 open-drain output 5.5.3.4 quasi-bidirectional mode explanation set gpiox_pmd (pm dn[1:0]) to 11b the gpiox port [n ] pin is in quasi-bidirectional mode and the i/o pin supports digital output and input function at the same time but the source current is only up to hundreds ua. before the digital input function is performed the corresponding bit in gpiox_dout must be set to 1. the quasi-bidire ctional output is common on the 80c51 and most of its derivatives. if the bit value in the corresponding bit [n] of gpiox_dout is 0, the pin drive a ?low? output on the pin. if the bit value in the co rresponding bit [n] of gpiox_dout is 1, the pin will check the pin value. if pin value is high, no action takes. if pin state is low, then pin will drive strong high with 2 clock cycles on the pin and then disable the strong output drive and then the pin status is control by internal pull-up resistor. note that the source current capability in quasi- bidirectional mode is only about 200ua to 30ua for vdd is form 5.0v to 2.5v. port 2 cpu clock delay input data port latch data pp p n vdd strong very weak weak figure 5-16 quasi-bidirectional i/o mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 243 - revision v1.06 5.5.4 register map r: read only, w: write only, r/w: both read and write register offset r/w description reset value gp_ba = 0x5000_4000 gpioa_pmd gp_ba+0x000 r/w gpio port a bit mode control 0xffff_ffff gpioa_offd gp_ba+0x004 r/w gpio port a bit off digital enable 0x0000_0000 gpioa_dout gp_ba+0x008 r/w gpio port a data output value 0x0000_ffff gpioa_dmask gp_ba+0x00c r/w gpio port a data output write mask 0x0000_0000 gpioa_pin gp_ba+0x010 r gpio port a pin value 0x0000_xxxx gpioa_dben gp_ba+0x014 r/w gpio port a de-bounce enable 0x0000_0000 gpioa_imd gp_ba+0x018 r/w gpio port a interrupt mode control 0x0000_0000 gpioa_ien gp_ba+0x01c r/w gpio port a interrupt enable 0x0000_0000 gpioa_isrc gp_ba+0x020 r/w gpio port a interrupt source flag 0xxxxx_xxxx gpiob_pmd gp_ba+0x040 r/w gpio port b bit mode enable 0xffff_ffff gpiob_offd gp_ba+0x044 r/w gpio port b bit off digital enable 0x0000_0000 gpiob_dout gp_ba+0x048 r/w gpio port b data output value 0x0000_ffff gpiob_dmask gp_ba+0x04c r/w gpio port b data output write mask 0x0000_0000 gpiob_pin gp_ba+0x050 r gpio port b pin value 0x0000_xxxx gpiob_dben gp_ba+0x054 r/w gpio port b de-bounce enable 0x0000_0000 gpiob_imd gp_ba+0x058 r/w gpio port b interrupt mode control 0x0000_0000 gpiob_ien gp_ba+0x05c r/w gpio port b interrupt enable 0x0000_0000 gpiob_isrc gp_ba+0x060 r/w gpio port b interrupt source flag 0xxxxx_xxxx gpioc_pmd gp_ba+0x080 r/w gpio port c bit mode enable 0xffff_ffff gpioc_offd gp_ba+0x084 r/w gpio port c bit off digital enable 0x0000_0000 gpioc_dout gp_ba+0x088 r/w gpio port c data output value 0x0000_ffff gpioc_dmask gp_ba+0x08c r/w gpio port c data output write mask 0x0000_0000 gpioc_pin gp_ba+0x090 r gpio port c pin value 0x0000_xxxx gpioc_dben gp_ba+0x094 r/w gpio port c de-bounce enable 0x0000_0000 gpioc_imd gp_ba+0x098 r/w gpio port c interrupt mode control 0x0000_0000 gpioc_ien gp_ba+0x09c r/w gpio port c interrupt enable 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 244 - revision v1.06 gpioc_isrc gp_ba+0x0a0 r/w gpio port c interrupt source flag 0xxxxx_xxxx gpiod_pmd gp_ba+0x0c0 r/w gpio port d bit mode enable 0xffff_ffff gpiod_offd gp_ba+0x0c4 r/w gpio port d bit off digital enable 0x0000_0000 gpiod_dout gp_ba+0x0c8 r/w gpio port d data output value 0x0000_ffff gpiod_dmask gp_ba+0x0cc r/w gpio port d data output write mask 0x0000_0000 gpiod_pin gp_ba+0x0d0 r gpio port d pin value 0x0000_xxxx gpiod_dben gp_ba+0x0d4 r/w gpio port d de-bounce enable 0x0000_0000 gpiod_imd gp_ba+0x0d8 r/w gpio port d interrupt mode control 0x0000_0000 gpiod_ien gp_ba+0x0dc r/w gpio port d interrupt enable 0x0000_0000 gpiod_isrc gp_ba+0x0e0 r/w gpio port d interrupt source flag 0xxxxx_xxxx gpioe_pmd gp_ba+0x100 r/w gpio port e bit mode enable 0xffff_ffff gpioe_offd gp_ba+0x104 r/w gpio port e bit off digital enable 0x0000_0000 gpioe_dout gp_ba+0x108 r/w gpio port e data output value 0x0000_ffff gpioe_dmask gp_ba+0x10c r/w gpio port e data output write mask 0x0000_0000 gpioe_pin gp_ba+0x110 r gpio port e pin value 0x0000_xxxx gpioe_dben gp_ba+0x114 r/w gpio port e de-bounce enable 0x0000_0000 gpioe_imd gp_ba+0x118 r/w gpio port e interrupt mode control 0x0000_0000 gpioe_ien gp_ba+0x11c r/w gpio port e interrupt enable 0x0000_0000 gpioe_isrc gp_ba+0x120 r/w gpio port e interrupt source flag 0xxxxx_xxxx dbncecon gp_ba+0x180 r/w de-bounce cycle control 0x0000_0020 gpioa0_dout gp_ba+0x200 r/w gpio port a.0 data output value (low density only) 0x0000_0001 gpioa1_dout gp_ba+0x204 r/w gpio port a.1 data output value (low density only) 0x0000_0001 gpioa2_dout gp_ba+0x208 r/w gpio port a.2 data output value (low density only) 0x0000_0001 gpioa3_dout gp_ba+0x20c r/w gpio port a.3 data output value (low density only) 0x0000_0001 gpioa4_dout gp_ba+0x210 r/w gpio port a.4 data output value (low density only) 0x0000_0001 gpioa5_dout gp_ba+0x214 r/w gpio port a.5 data output value (low density only) 0x0000_0001 gpioa6_dout gp_ba+0x218 r/w gpio port a.6 data output value (low density only) 0x0000_0001 gpioa7_dout gp_ba+0x21c r/w gpio port a.7 data output value (low density only) 0x0000_0001 gpioa8_dout gp_ba+0x220 r/w gpio port a.8 data output value (low density only) 0x0000_0001 gpioa9_dout gp_ba+0x224 r/w gpio port a.9 data output value (low density only) 0x0000_0001 gpioa10_dout gp_ba+0x228 r/w gpio port a.10 data output value (low density only) 0x0000_0001 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 245 - revision v1.06 gpioa11_dout gp_ba+0x22c r/w gpio port a.11 data output value (low density only) 0x0000_0001 gpioa12_dout gp_ba+0x230 r/w gpio port a.12 data output value (low density only) 0x0000_0001 gpioa13_dout gp_ba+0x234 r/w gpio port a.13 data output value (low density only) 0x0000_0001 gpioa14_dout gp_ba+0x238 r/w gpio port a.14 data output value (low density only) 0x0000_0001 gpioa15_dout gp_ba+0x23c r/w gpio port a.15 data output value (low density only) 0x0000_0001 gpiob0_dout gp_ba+0x240 r/w gpio port b.0 data output value (low density only) 0x0000_0001 gpiob1_dout gp_ba+0x244 r/w gpio port b.1 data output value (low density only) 0x0000_0001 gpiob2_dout gp_ba+0x248 r/w gpio port b.2 data output value (low density only) 0x0000_0001 gpiob3_dout gp_ba+0x24c r/w gpio port b.3 data output value (low density only) 0x0000_0001 gpiob4_dout gp_ba+0x250 r/w gpio port b.4 data output value (low density only) 0x0000_0001 gpiob5_dout gp_ba+0x254 r/w gpio port b.5 data output value (low density only) 0x0000_0001 gpiob6_dout gp_ba+0x258 r/w gpio port b.6 data output value (low density only) 0x0000_0001 gpiob7_dout gp_ba+0x25c r/w gpio port b.7 data output value (low density only) 0x0000_0001 gpiob8_dout gp_ba+0x260 r/w gpio port b.8 data output value (low density only) 0x0000_0001 gpiob9_dout gp_ba+0x264 r/w gpio port b.9 data output value (low density only) 0x0000_0001 gpiob10_dout gp_ba+0x268 r/w gpio port b.10 data output value (low density only) 0x0000_0001 gpiob11_dout gp_ba+0x26c r/w gpio port b.11 data output value (low density only) 0x0000_0001 gpiob12_dout gp_ba+0x270 r/w gpio port b.12 data output value (low density only) 0x0000_0001 gpiob13_dout gp_ba+0x274 r/w gpio port b.13 data output value (low density only) 0x0000_0001 gpiob14_dout gp_ba+0x278 r/w gpio port b.14 data output value (low density only) 0x0000_0001 gpiob15_dout gp_ba+0x27c r/w gpio port b.15 data output value (low density only) 0x0000_0001 gpioc0_dout gp_ba+0x280 r/w gpio port c.0 data output value (low density only) 0x0000_0001 gpioc1_dout gp_ba+0x284 r/w gpio port c.1 data output value (low density only) 0x0000_0001 gpioc2_dout gp_ba+0x288 r/w gpio port c.2 data output value (low density only) 0x0000_0001 gpioc3_dout gp_ba+0x28c r/w gpio port c.3 data output value (low density only) 0x0000_0001 gpioc4_dout gp_ba+0x290 r/w gpio port c.4 data output value (low density only) 0x0000_0001 gpioc5_dout gp_ba+0x294 r/w gpio port c.5 data output value (low density only) 0x0000_0001 gpioc6_dout gp_ba+0x298 r/w gpio port c.6 data output value (low density only) 0x0000_0001 gpioc7_dout gp_ba+0x29c r/w gpio port c.7 data output value (low density only) 0x0000_0001 gpioc8_dout gp_ba+0x2a0 r/w gpio port c.8 data output value (low density only) 0x0000_0001 gpioc9_dout gp_ba+0x2a4 r/w gpio port c.9 data output value (low density only) 0x0000_0001 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 246 - revision v1.06 gpioc10_dout gp_ba+0x2a8 r/w gpio port c.10 data output value (low density only) 0x0000_0001 gpioc11_dout gp_ba+0x2ac r/w gpio port c.11 data output value (low density only) 0x0000_0001 gpioc12_dout gp_ba+0x2b0 r/w gpio port c.12 data output value (low density only) 0x0000_0001 gpioc13_dout gp_ba+0x2b4 r/w gpio port c.13 data output value (low density only) 0x0000_0001 gpioc14_dout gp_ba+0x2b8 r/w gpio port c.14 data output value (low density only) 0x0000_0001 gpioc15_dout gp_ba+0x2bc r/w gpio port c.15 data output value (low density only) 0x0000_0001 gpiod0_dout gp_ba+0x2c0 r/w gpio port d.0 data output value (low density only) 0x0000_0001 gpiod1_dout gp_ba+0x2c4 r/w gpio port d.1 data output value (low density only) 0x0000_0001 gpiod2_dout gp_ba+0x2c8 r/w gpio port d.2 data output value (low density only) 0x0000_0001 gpiod3_dout gp_ba+0x2cc r/w gpio port d.3 data output value (low density only) 0x0000_0001 gpiod4_dout gp_ba+0x2d0 r/w gpio port d.4 data output value (low density only) 0x0000_0001 gpiod5_dout gp_ba+0x2d4 r/w gpio port d.5 data output value (low density only) 0x0000_0001 gpiod6_dout gp_ba+0x2d8 r/w gpio port d.6 data output value (low density only) 0x0000_0001 gpiod7_dout gp_ba+0x2dc r/w gpio port d.7 data output value (low density only) 0x0000_0001 gpiod8_dout gp_ba+0x2e0 r/w gpio port d.8 data output value (low density only) 0x0000_0001 gpiod9_dout gp_ba+0x2e4 r/w gpio port d.9 data output value (low density only) 0x0000_0001 gpiod10_dout gp_ba+0x2e8 r/w gpio port d.10 data output value (low density only) 0x0000_0001 gpiod11_dout gp_ba+0x2ec r/w gpio port d.11 data output value (low density only) 0x0000_0001 gpiod12_dout gp_ba+0x2f0 r/w gpio port d.12 data output value (low density only) 0x0000_0001 gpiod13_dout gp_ba+0x2f4 r/w gpio port d.13 data output value (low density only) 0x0000_0001 gpiod14_dout gp_ba+0x2f8 r/w gpio port d.14 data output value (low density only) 0x0000_0001 gpiod15_dout gp_ba+0x2fc r/w gpio port d.15 data output value (low density only) 0x0000_0001 gpioe5_dout gp_ba+0x314 r/w gpio port e.5 data output value (low density only) 0x0000_0001 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 247 - revision v1.06 5.5.5 register description gpio port [a/b/c/d/e] i/o mode control (gpiox_pmd) register offset r/w description reset value gpioa_pmd gp_ba+0x000 r/w gpio port a pin i/o mode control 0xffff_ffff gpiob_pmd gp_ba+0x040 r/w gpio port b pin i/o mode control 0xffff_ffff gpioc_pmd gp_ba+0x080 r/w gpio port c pin i/o mode control 0xffff_ffff gpiod_pmd gp_ba+0x0c0 r/w gpio port d pin i/o mode control 0xffff_ffff gpioe_pmd gp_ba+0x100 r/w gpio port e pin i/o mode control 0xffff_ffff 31 30 29 28 27 26 25 24 pmd15 pmd14 pmd13 pmd12 23 22 21 20 19 18 17 16 pmd11 pmd10 pmd9 pmd8 15 14 13 12 11 10 9 8 pmd7 pmd6 pmd5 pmd4 7 6 5 4 3 2 1 0 pmd3 pmd2 pmd1 pmd0 bits descriptions [2n+1:2n] pmdn gpiox i/o pin[n] mode control determine each i/o type of gpiox pins. 00 = gpio port [n] pin is in input mode 01 = gpio port [n] pin is in output mode 10 = gpio port [n] pin is in open-drain mode 11 = gpio port [n] pin is in quasi-bidirectional mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 248 - revision v1.06 gpio port [a/b/c/d/e] bit off digi tal resistor enable (gpiox_offd) register offset r/w description reset value gpioa_offd gp_ba+0x004 r/w gpio port a pin off digital enable 0x0000_0000 gpiob_offd gp_ba+0x044 r/w gpio port b pin off digital enable 0x0000_0000 gpioc_offd gp_ba+0x084 r/w gpio port c pin off digital enable 0x0000_0000 gpiod_offd gp_ba+0x0c4 r/w gpio port d pin off digital enable 0x0000_0000 gpioe_offd gp_ba+0x104 r/w gpio port e pin off digital enable 0x0000_0000 31 30 29 28 27 26 25 24 offd 23 22 21 20 19 18 17 16 offd 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bits descriptions [16:31] offd gpiox pin[n] off digital input path enable each of these bits is used to control if the input path of corresponding gpio pin is disabled. if input is analog signal, users can off digital input path to avoid creepage 1 = disable io digital input pat h (digital input tied to low) 0 = enable io digital input path [0:15] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 249 - revision v1.06 gpio port [a/b/c/d/e] data output value (gpiox_dout) register offset r/w description reset value gpioa_dout gp_ba+0x008 r/w gpio port a data output value 0x0000_ffff gpiob_dout gp_ba+0x048 r/w gpio port b data output value 0x0000_ffff gpioc_dout gp_ba+0x088 r/w gpio port c data output value 0x0000_ffff gpiod_dout gp_ba+0x0c8 r/w gpio port d data output value 0x0000_ffff gpioe_dout gp_ba+0x108 r/w gpio port e data output value 0x0000_ffff 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 dout[15:8] 7 6 5 4 3 2 1 0 dout[7:0] bits descriptions [31:16] reserved reserved [n] dout[n] gpiox pin[n] output value each of these bits control the status of a gpio pin when the gpio pin is configures as output, open-drain and quasi-mode. 1 = gpio port [a/b/c/d/e] pin[n] will drive high if the gpio pin is configures as output, open-drain and quasi-mode. 0 = gpio port [a/b/c/d/e] pin[n] will drive lo w if the gpio pin is configures as output, open-drain and quasi-mode. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 250 - revision v1.06 gpio port [a/b/c/d/e] data ou tput write mask (gpiox _dmask) register offset r/w description reset value gpioa_dmask gp_ba+0x00c r/w gpio port a data output write mask 0xxxxx_0000 gpiob_dmask gp_ba+0x04c r/w gpio port b data output write mask 0xxxxx_0000 gpioc_dmask gp_ba+0x08c r/w gpio port c data output write mask 0xxxxx_0000 gpiod_dmask gp_ba+0x0cc r/w gpio port d data output write mask 0xxxxx_0000 gpioe_dmask gp_ba+0x10c r/w gpio port e data output write mask 0xxxxx_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 dmask[15:8] 7 6 5 4 3 2 1 0 dmask[7:0] bits descriptions [31:16] reserved reserved [n] dmask[n] port [a/b/c/d/e] data output write mask these bits are used to protect the corres ponding register of gpiox_dout bit[n] . when set the dmask bit[n] to 1, the corre sponding gpiox_doutn bit is protected. the write signal is masked, write data to the protect bit is ignored 1 = the corresponding gpiox_dout[n] bit is protected 0 = the corresponding gpiox_dout[n] bit can be updated numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 251 - revision v1.06 gpio port [a/b/c/d/e] pin value (gpiox _pin) register offset r/w description reset value gpioa_pin gp_ba+0x010 r gpio port a pin value 0x0000_xxxx gpiob_pin gp_ba+0x050 r gpio port b pin value 0x0000_xxxx gpioc_pin gp_ba+0x090 r gpio port c pin value 0x0000_xxxx gpiod_pin gp_ba+0x0d0 r gpio port d pin value 0x0000_xxxx gpioe_pin gp_ba+0x110 r gpio port e pin value 0x0000_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 pin[15:8] 7 6 5 4 3 2 1 0 pin[7:0] bits descriptions [31:16] reserved reserved [n] pin[n] port [a/b/c/d/e] pin values each bit of the register reflects the actual st atus of the respective gpio pin if bit is 1, it indicates the corresponding pin status is high, else the pin status is low numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 252 - revision v1.06 gpio port [a/b/c/d/e] de-bounce enable (gpiox _dben) register offset r/w description reset value gpioa_dben gp_ba+0x014 r/w gpio port a de-bounce enable 0xxxxx_0000 gpiob_dben gp_ba+0x054 r/w gpio port b de-bounce enable 0xxxxx_0000 gpioc_dben gp_ba+0x094 r/w gpio port c de-bounce enable 0xxxxx_0000 gpiod_dben gp_ba+0x0d4 r/w gpio port d de-bounce enable 0xxxxx_0000 gpioe_dben gp_ba+0x114 r/w gpio port e de-bounce enable 0xxxxx_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 dben[15:8] 7 6 5 4 3 2 1 0 dben[7:0] bits descriptions [31:16] reserved reserved [n] dben[n] port [a/b/c/d/e] input signal de-bounce enable dben[n]used to enable the de-bounce functi on for each corresponding bit. if the input signal pulse width can?t be sampled by c ontinuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. the de-bounce clock source is controlled by dbncecon[4], one de-bounce sample cycle is controlled by dbncecon[3:0] the dben[n] is used for ?edge-trigger? interrupt only, and ignored for ?level trigger? interrupt 1 = the bit[n] de-bounce function is enabled 0 = the bit[n] de-bounce function is disabled the de-bounce function is valid for edge triggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 253 - revision v1.06 gpio port [a/b/c/d/e] interrupt mode control (gpiox _imd) register offset r/w description reset value gpioa_imd gp_ba+0x018 r/w gpio port a interrupt mode control 0xxxxx_0000 gpiob_imd gp_ba+0x058 r/w gpio port b interrupt mode control 0xxxxx_0000 gpioc_imd gp_ba+0x098 r/w gpio port c interrupt mode control 0xxxxx_0000 gpiod_imd gp_ba+0x0d8 r/w gpio port d interrupt mode control 0xxxxx_0000 gpioe_imd gp_ba+0x118 r/w gpio port e interrupt mode control 0xxxxx_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 imd[15:8] 7 6 5 4 3 2 1 0 imd[7:0] bits descriptions [31:16] reserved reserved [n] imd[n] port [a/b/c/d/e] edge or level detection interrupt control imd[n] is used to control the interrupt is by level trigger or by edge trigger. if the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. if the interrupt is by level trigger, the input source is sampled by one hclk clock and generates the interrupt. 1 = level trigger interrupt 0 = edge trigger interrupt if set pin as the level trigger interrupt, then only one level can be set on the registers gpiox_ien. if set both the level to trigger interrupt, the setting is ignored and no interrupt will occur the de-bounce function is valid for edge tri ggered interrupt. if the interrupt mode is level triggered, the de-bounce enable bit is ignored. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 254 - revision v1.06 gpio port [a/b/c/d] interrupt enable control (gpiox _ien) register offset r/w description reset value gpioa_ien gp_ba+0x01c r/w gpio port a interrupt enable 0x0000_0000 gpiob_ien gp_ba+0x05c r/w gpio port b interrupt enable 0x0000_0000 gpioc_ien gp_ba+0x09c r/w gpio port c interrupt enable 0x0000_0000 gpiod_ien gp_ba+0x0dc r/w gpio port d interrupt enable 0x0000_0000 gpioe_ien gp_ba+0x11c r/w gpio port e interrupt enable 0x0000_0000 31 30 29 28 27 26 25 24 ir_en[15:8] 23 22 21 20 19 18 17 16 ir_en[7:0] 15 14 13 12 11 10 9 8 if_en[15:8] 7 6 5 4 3 2 1 0 if_en[7:0] bits descriptions [n+16] ir_en[n] port [a/b/c/d/e] interrupt enable by input rising edge or input level high ir_en[n] used to enable the interrupt for each of the corresponding input gpio_pin[n]. set bit to 1 also enable the pin wakeup function when set the ir_eb[n] bit to 1: if the interrupt is level trigger, the input pi n[n] state at level ?high? will generate the interrupt. if the interrupt is edge trigger, the input pin[n] state change from ?low-to-high? will generate the interrupt. 1 = enable the pin[n] level-high or low-to-high interrupt 0 = disable the pin[n] level-high or low-to-high interrupt [n] if_en[n] port [a/b/c/d/e] interrupt enable by input falling edge or input level low if_en[n] used to enable the interrupt for each of the corresponding input gpio_pin[n]. set bit to 1 also enable the pin wakeup function when set the if_eb[n] bit to 1: if the interrupt is level trigger, the input pin[n] state at level ?low? will generate the interrupt. if the interrupt is edge trigger, the input pin[n] state change from ?high-to-low? will generate the interrupt. 1 = enable the pin[n] state low-level or high-to-low change interrupt 0 = disable the pin[n] state low-level or high-to-low change interrupt numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 255 - revision v1.06 gpio port [a/b/c/d/e] interrupt trigger source (gpiox _isrc) register offset r/w description reset value gpioa_isrc gp_ba+0x020 r/w gpio port a interrupt trigger source indicator 0x0000_0000 gpiob_isrc gp_ba+0x060 r/w gpio port b interrupt trigger source indicator 0x0000_0000 gpioc_isrc gp_ba+0x0a0 r/w gpio port c interrupt trigger source indicator 0x0000_0000 gpiod_isrc gp_ba+0x0e0 r/w gpio port d interrupt trigger source indicator 0x0000_0000 gpioe_isrc gp_ba+0x120 r/w gpio port e interrupt trigger source indicator 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 if_ isrc[15:8] 7 6 5 4 3 2 1 0 if_ isrc[7:0] bits descriptions [31:16] reserved reserved [n] isrc[n] port [a/b/c/d/e] interrupt trigger source indicator read : 1 = indicates gpiox[n] generate an interrupt 0 = no interrupt at gpiox[n] write : 1= clear the correspond pending interrupt 0= no action numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 256 - revision v1.06 interrupt de-bounce cycle control (dbncecon) register offset r/w description reset value dbncecon gp_ba+0x180 r/w external interrupt de-bounce control 0x0000_0020 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved iclk_on dbclksrc dbclksel bits descriptions [5] iclk_on interrupt clock on mode set this bit to 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled 1 = interrupt generated circuit clock always enable 0 = disable the clock if the gpioa/b/c/d/e[n] interrupt is disabled [4] dbclksrc de-bounce counter clock source select 1 = de-bounce counter clock source is the internal 10 khz clock 0 = de-bounce counter clock source is the hclk [3:0] dbclksel de-bounce sampling cycle selection dbclksel description 0 sample interrupt input once per 1 clocks 1 sample interrupt input once per 2 clocks 2 sample interrupt input once per 4 clocks 3 sample interrupt input once per 8 clocks 4 sample interrupt input once per 16 clocks 5 sample interrupt input once per 32 clocks 6 sample interrupt input once per 64 clocks 7 sample interrupt input once per 128 clocks 8 sample interrupt input once per 256 clocks 9 sample interrupt input once per 2*256 clocks 10 sample interrupt input once per 4*256clocks 11 sample interrupt input once per 8*256 clocks numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 257 - revision v1.06 12 sample interrupt input once per 16*256 clocks 13 sample interrupt input once per 32*256 clocks 14 sample interrupt input once per 64*256 clocks 15 sample interrupt input once per 128*256 clocks numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 258 - revision v1.06 gpio port [a/b/c/d/e] i/o bit output control (gpioxx_dout) register offset r/w description reset value gpioax_dout gp_ba+0x200 - gp_ba+0x23c r/w gpio port a pin i/o bit output control 0x0000_0001 gpiobx_dout gp_ba+0x240 - gp_ba+0x27c r/w gpio port b pin i/o bit output control 0x0000_0001 gpiocx_dout gp_ba+0x280 - gp_ba+0x2bc r/w gpio port c pin i/o bit output control 0x0000_0001 gpiodx_dout gp_ba+0x2c0 - gp_ba+0x2fc r/w gpio port d pin i/o bit output control 0x0000_0001 gpioe5_dout gp_ba+0x314 r/w gpio port e pin i/o bit output control 0x0000_0001 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved gpioxx_dou t bits descriptions [0] gpioxx_dout gpioxx i/o pin bit output control set this bit can control one gpio pin output value 1 = set corresponding gpio bit to high 0 = set corresponding gpio bit to low for example: write gpioa0_dout will reflect the written value to bit gpioa_dout[0], read gpioa0_dout will return the value of gpioa_pin[0] numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 259 - revision v1.06 5.6 i 2 c serial interface controller (master/slave) (i 2 c) 5.6.1 overview i 2 c is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more mast ers attempt to control the bus simultaneously. serial, 8-bit oriented bi-directional data transfers can be made up 1.0 mbps. data is transferred between a master and a slave synchronously to scl on the sda line on a byte-by-byte basis. each data byte is 8 bits long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to the figure 5-17 fo r more detail i 2 c bus timing. figure 5-17 i 2 c bus timing the device?s on-chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomousl y. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda and scl. pull up resistor is needed for i 2 c operation as these are open drain pins. when the i/o pins are used as i 2 c port, user must set t he pins function to i 2 c in advance. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 260 - revision v1.06 5.6.2 features the i 2 c bus uses two wires (sda and scl) to transf er information between devices connected to the bus. the main features of the bus are: z master/slave up to 1mbit/s z bidirectional data transfer between masters and slaves z multi-master bus (no central master) z arbitration between simultaneously transmitting masters without corruption of serial data on the bus z serial clock synchronization allows devices with different bit rates to communicate via one serial bus z serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer z built-in a 14-bit time-out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer-out counter overflows. z external pull-up are needed for high output z programmable clocks allow versatile rate control z supports 7-bit addressing mode z i 2 c-bus controllers support multiple address recognition ( four slave address with mask option) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 261 - revision v1.06 5.6.3 function description 5.6.3.1 i 2 c protocol normally, a standard communication consists of four parts: 1) start or repeated start signal generation 2) slave address and r/w bit transfer 3) data transfer 4) stop signal generation figure 5-18 i 2 c protocol 5.6.3.2 data transfer on the i 2 c-bus a master-transmitter addressing a slave receiver with a 7-bit address the transfer direction is not changed a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition ?0? : write s slave address r/w a data a data a/a p from master to slave from slave to master data transfer (n bytes + acknowlegde) figure 5-19 master transmits data to slave a master reads a slave immediately after the first byte (address) the transfer direction is changed ?1? : read s slave address r/w a data a data a/a p data transfer (n bytes + acknowlegde) figure 5-20 master reads data from slave numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 262 - revision v1.06 5.6.3.3 start or repeated start signal whe n the bus is free/idle, meaning no master device is engaging the bus (both scl and sda lines are high), a master can initiate a transfer by sending a start signal. a start signal, usually referred to as the s-bit, is defined as a high to low transition on the sda line while scl is high. the start signal denotes the beginning of a new data transfer. a repeated start (sr) is no stop signal between two start signals. the master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. stop signal the master can terminate the communication by generating a stop signal. a stop signal, usually referred to as the p-bit, is defined as a low to high transition on the sda line while scl is high. figure 5-21 start and stop condition 5.6.3.4 slave address transfer the first byte of data transferred by the master immediately after the start signal is the slave address. this is a 7-bits calling address follow ed by a rw bit. the rw bit signals the slave the data transfer direction. no two slaves in the sy stem can have the same ad dress. only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the sda low at the 9th scl clock cycle. 5.6.3.5 data transfer once su ccessful slave addressing has been achi eved, the data transfer can proceed on a byte- by-byte basis in the direction specified by the rw bit sent by the master. each transferred byte is followed by an acknowledge bit on the 9th sc l clock cycle. if the slave signals a not acknowledge (nack), the master can generate a stop signal to abort the data transfer or generate a repeated start signal and start a new transfer cycle. if the master, as the receiving device, does no t acknowledge (nack) the slave, the slave releases the sda line for the master to generate a stop or repeated start signal. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 263 - revision v1.06 sda scl data line stable; data valid change of data allowed figure 5-22 bit transfer on the i 2 c bus data output by transmitter scl from master start condition acknowlegde data output by receiver s 12 8 9 clock pulse for acknowledgement not acknowlegde figure 5-23 acknowledge on the i 2 c bus numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 264 - revision v1.06 5.6.4 protocol registers the cpu interfaces to the i 2 c port through the following thirteen special function registers: i2con (control register), i2cstatus (status register), i2cdat (data register), i2caddrn (address registers, n=0~3), i2cadmn (address mask regi sters, n=0~3), i2clk (clock rate register) and i2ctoc (time-out counter register). all bit 31~ bit 8 of these i 2 c special function registers are reserved. these bits do not have any functions and are all zero if read back. when i 2 c port is enabled by setting ens1 (i2con [6]) to high, the internal states will be controlled by i2con and i 2 c logic hardware. once a new status code is generated and stored in i2cstatus, the i 2 c interrupt flag bit si (i2con [3]) will be set automatically. if the enable interrupt bit ei (i2con [7]) is set high at this time, the i 2 c interrupt will be generated. the bit field i2cstatus[7:3] stores the internal state code, the lowest 3 bits of i2cstatus are always zero and the content keeps stable until si is cleared by software. the base address is 4002_0000 and 4012_0000. 5.6.4.1 address regist er s (i2caddr) i 2 c port is equipped with four slave address registers i2caddrn (n=0~3). the contents of the register are irrelevant when i 2 c is in master mode. in the slave mode, the bit field i2caddrn[7:1] must be loaded with the chip?s own slave address. the i 2 c hardware will react if the contents of i2caddrn are matched with the received slave address. the i 2 c ports support the ?general call? function. if the gc bit (i2caddrn [0]) is set the i 2 c port hardware will respond to general call address (00h). clear gc bit to disable general call function. when gc bit is set and the i 2 c is in slave mode, it can receive the general call address by 00h after master send general call address to i 2 c bus, then it will follow status of gc mode. i 2 c bus controllers support multiple address re cognition with four address mask registers i2cadmn (n=0~3). when the bit in the address mask register is set to one, it means the received corresponding address bit is don?t-care. if the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 5.6.4.2 data register (i2cdat) this regi ster contains a byte of serial data to be transmitted or a byte which just has been received. the cpu can read from or write to this 8- bit (i2cdat [7:0]) directly while it is not in the process of shifting a byte. when i 2 c is in a defined state and the serial interrupt flag (si) is set. data in i2cdat [7:0] remains stable as long as si bit is set. while data is being shifted out, data on the bus is simultaneously being shifted in; i2cda t [7:0] always contains the last data byte present on the bus. thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in i2cdat [7:0]. i2cdat [7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the i 2 c hardware and cannot be accessed by the cp u. serial data is shifted through the acknowledge bit into i2cdat [7:0] on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into i2cdat [7:0], t he serial data is available in i2cdat [7:0], and the acknowledge bit (ack or nack) is returned by the control logic during the ninth clock pulse. serial data is shifted out from i2cdat [7:0] on the falling edges of scl clock pulses, and is shifted into i2cdat [7:0] on the ri sing edges of scl clock pulses. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 265 - revision v1.06 i2cdat.7 i2c data register: shifting direction i2cdat.6 i2cdat.5 i2cdat.4 i2cdat.3 i2cdat.2 i2cdat.1 i2cdat.0 figure 5-24 i 2 c data shifting direction 5.6.4.3 control register (i2con) the cp u can read from and write to this 8-bit fiel d of i2con [7:0] directly. two bits are affected by hardware: the si bit is set when the i 2 c hardware requests a serial interrupt, and the sto bit is cleared when a stop condition is present on the bus. the sto bit is also cleared when ens1 = 0. ei enable interrupt. ensi set to enable i 2 c serial function controller. when ensi=1 the i 2 c serial function enables. the multi function pin function of sda and scl must be set to i 2 c function. sta i 2 c start control bit. setting sta to logic 1 to enter master mode, the i 2 c hardware sends a start or repeat start condition to bus when the bus is free. sto i 2 c stop control bit. in master mode, setti ng sto to transmit a stop condition to bus then i 2 c hardware will check the bus condition if a stop condition is detected this flag will be cleared by hardware automatically. in a slave mode, setting sto resets i 2 c hardware to the defined ?not addressed? slave mode. th is means it is no longer in the slave receiver mode to receive data from the master transmit device. si i 2 c interrupt flag. when a new i 2 c state is present in the i2cstatus register, the si flag is set by hardware, and if bit ei (i2con [7]) is set, the i 2 c interrupt is requested. si must be cleared by software. clear si is by writing 1 to this bit. all states are listed in section 5.6.6 aa assert acknowledge control bit. when aa=1 prior to address or data received, an acknowledged (low level to sda) will be returned during the acknowledge clock pulse on the scl line when 1.) a slave is acknowledging the address sent from master, 2.) the receiver devices are acknowledging the data sent by transmitter. when aa=0 prior to address or data received, a not acknowledged (high level to sda) will be returned during the acknowledge clock pulse on the scl line. 5.6.4.4 status register (i2cstatus) i2cstatus [ 7:0] is an 8-bit read-only register. the three least significant bits are always 0. the bit field i2cstatus [7:3] contain the status code. there are 26 possible status codes, all states are listed in section 5.6.6. when i2cstatus [7:0] contains f8h, no serial interrupt is requested. all other i2cstatus [7:3] values correspond to defined i 2 c states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is pr esent in i2cstatus[7:3] one cycle after si is set by hardware and is stil l present one cycle after si has been reset by software. in addition, state 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. to recover i 2 c numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 266 - revision v1.06 from bus error, sto should be set and si shoul d be clear to enter not addressed slave mode. then clear sto to release bus and to wait new communication. i 2 c bus can not recognize stop condition during this action when bus error occurs. 5.6.4.5 i 2 c clock baud rate bits (i2clk) the data baud rate of i 2 c is determines by i2clk [7:0] register when i 2 c is in a master mode. it is not important when i 2 c is in a slave mode. in the slave modes, i 2 c will automatically synchronize with any clock frequency up to 1mhz from master i 2 c device. the data baud rate of i 2 c setting is data baud rate of i 2 c = (system clock) / (4x (i2clk [7:0] +1)). if system clock = 16 mhz, the i2clk [7:0] = 40 (28h), so data baud rate of i 2 c = 16 mhz/ (4x (40 +1)) = 97.5 kbits/sec. the block diagram is showed as figure 5-25. 5.6.4.6 the i 2 c time-out counter register (i2ctoc) there is a 14-bit time-out counter which can be used to deal with the i 2 c bus hang-up. if the time- out counter is enabled, the counter starts up counting until it overflows (tif=1) and generates i 2 c interrupt to cpu or stops counting by clearing enti to 0. when time-out counter is enabled, setting flag si to high will reset counter and re-start up counting after si is cleared. if i 2 c bus hangs up, it causes the i2cstatus and flag si ar e not updated for a period, the 14-bit time-out counter may overflow and acknowledge cpu the i 2 c interrupt. refer to the figure 5-25 for the 14- bit time-out counter. use r may write 1 to clear tif to zero. figure 5-25: i 2 c time-out count block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 267 - revision v1.06 5.6.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value i2c0_ba = 0x4002_0000 i2c1_ba = 0x4012_0000 i2con i2cx_ba+0x00 r/w i 2 c control register 0x0000_0000 i2caddr0 i2cx_ba+0x04 r/w i 2 c slave address register0 0x0000_0000 i2cdat i2cx_ba+0x08 r/w i 2 c data register 0x0000_0000 i2cstatus i2cx_ba+0x0c r i 2 c status register 0x0000_00f8 i2clk i2cx_ba+0x10 r/w i 2 c clock divided register 0x0000_0000 i2ctoc i2cx_ba+0x14 r/w i 2 c time out control register 0x0000_0000 i2caddr1 i2cx_ba+0x18 r/w i 2 c slave address register1 0x0000_0000 i2caddr2 i2cx_ba+0x1c r/w i 2 c slave address register2 0x0000_0000 i2caddr3 i2cx_ba+0x20 r/w i 2 c slave address register3 0x0000_0000 i2cadm0 i2cx_ba+0x24 r/w i 2 c slave address mask register0 0x0000_0000 i2cadm1 i2cx_ba+0x28 r/w i 2 c slave address mask register1 0x0000_0000 i2cadm2 i2cx_ba+0x2c r/w i 2 c slave address mask register2 0x0000_0000 i2cadm3 i2cx_ba+0x30 r/w i 2 c slave address mask register3 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 268 - revision v1.06 5.6.6 register description i 2 c control register (i2con) register offset r/w description reset value i2con i2c_ba+0x00 r/w i 2 c control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 ei ensi sta sto si aa reserved bits descriptions [31:8] reserved reserved [7] ei enable interrupt 1 = enable i 2 c interrupt 0 = disable i 2 c interrupt [6] ensi i 2 c controller enable bit 1 = enable 0 = disable set to enable i 2 c serial function controller. when ensi=1 the i 2 c serial function enables. the multi-function pin function of sda and scl must set to i 2 c function first. [5] sta i 2 c start control bit setting sta to logic 1 to enter master mode, the i 2 c hardware sends a start or repeat start condition to bus when the bus is free. [4] sto i 2 c stop control bit in master mode, setting sto to transmit a stop condition to bus then i 2 c hardware will check the bus condition if a stop condi tion is detected this bit will be cleared by hardware automatically. in a slave mode, setting sto resets i 2 c hardware to the defined ?not addressed? slave mode. this means it is no longer in the slave receiver mode to receive data from the master transmit device. [3] si i 2 c interrupt flag when a new i 2 c state is present in the i2cstatus register, the si flag is set by hardware, and if bit ei (i2con [7]) is set, the i 2 c interrupt is requested. si must be cleared by software. clear si is by writing 1 to this bit. [2] aa assert acknowledge control bit when aa=1 prior to address or data received, an acknowledged (low level to sda) will numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 269 - revision v1.06 be returned during the acknowledge clock pulse on the scl line when 1.) a slave is acknowledging the address sent from ma ster, 2.) the receiver devices are acknowledging the data sent by transmitte r. when aa=0 prior to address or data received, a not acknowledged (high leve l to sda) will be returned during the acknowledge clock pulse on the scl line. [1:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 270 - revision v1.06 i 2 c data register (i2cdat) register offset r/w description reset value i2cdat i2c_ba+0x08 r/w i 2 c data register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2cdat[7:0] bits descriptions [31:8] reserved reserved [7:0] i2cdat i 2 c data register bit [7:0] is located with the 8-bit transferred data of i 2 c serial port. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 271 - revision v1.06 i 2 c status register (i2cstatus ) register offset r/w description reset value i2cstatus i2c_ba+0x0c r/w i 2 c status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2cstatus[7:3] 0 0 0 bits descriptions [31:8] reserved reserved [7:0] i2cstatus i 2 c status register the status register of i 2 c: the three least significant bits are always 0. the five most significant bits contain the status code. there are 26 possible status codes. when i2cstatus contains f8h, no serial interrupt is requested. all other i2cstatus values correspond to defined i 2 c states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in i2cstatus one cycle after si is set by hardware and is still present one cycle after si has been reset by software. in addition, states 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal position in the format ion frame. example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 272 - revision v1.06 i 2 c clock divided register (i2clk) register offset r/w description reset value i2clk i2c_ba+0x10 r/w i 2 c clock divided register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2clk[7:0] bits descriptions [31:8] reserved reserved [7:0] i2clk i 2 c clock divided register the i 2 c clock rate bits: data baud rate of i 2 c = (system clock) / (4x (i2clk+1)). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 273 - revision v1.06 i 2 c time-out counter register (i2ctoc) register offset r/w description reset value i2ctoc i2c_ba+0x14 r/w i 2 c time-out counter register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved enti div4 tif bits descriptions [31:3] reserved reserved [2] enti time-out counter is enabled/disable 1 = enable 0 = disable when enable, the 14 bit time-out counter w ill start counting when si is clear. setting flag si to high will reset counter and re-start up counting after si is cleared. [1] div4 time-out counter input clock is divided by 4 1 = enable 0 = disable when enable, the time-out period is extend 4 times. [0] tif time-out flag 1 = time-out flag is set by h/w. it can interrupt cpu. 0 = s/w can clear the flag. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 274 - revision v1.06 i 2 c slave address register (i2caddrx) register offset r/w description reset value i2caddr0 i2c_ba+0x04 r/w i 2 c slave address register0 0x0000_0000 i2caddr1 i2c_ba+0x18 r/w i 2 c slave address register1 0x0000_0000 i2caddr2 i2c_ba+0x1c r/w i 2 c slave address register2 0x0000_0000 i2caddr3 i2c_ba+0x20 r/w i 2 c slave address register3 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2caddr[7:1] gc bits descriptions [31:8] reserved reserved [7:1] i2caddr i 2 c address register the content of this register is irrelevant when i 2 c is in master mode. in the slave mode, the seven most significant bits must be loaded with the chip?s own address. the i 2 c hardware will react if either of the address is matched. [0] gc general call function 0 = disable general call function. 1 = enable general call function. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 275 - revision v1.06 i 2 c slave address mask register (i2cadmx) register offset r/w description reset value i2cadm0 i2c_ba+0x24 r/w i 2 c slave address mask register0 0x0000_0000 i2cadm1 i2c_ba+0x28 r/w i 2 c slave address mask register1 0x0000_0000 i2cadm2 i2c_ba+0x2c r/w i 2 c slave address mask register2 0x0000_0000 i2cadm3 i2c_ba+0x30 r/w i 2 c slave address mask register3 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2cadm[7:1] reserved bits descriptions [31:8] reserved reserved [7:1] i2cadm i 2 c address mask register 1 = mask enable (the received corresponding address bit is don?t care.) 0 = mask disable (the received corresponding register bit should be exact the same as address register.) i 2 c bus controllers support multiple addre ss recognition with four address mask register. when the bit in the address mask regist er is set to one, it means the received corresponding address bit is don?t-care. if the bi t is set to zero, that means the received corresponding register bit should be exact the same as address register. [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 276 - revision v1.06 5.6.7 modes of operation the on-chip i 2 c ports support five operation modes, mast er transmitter, master receiver, slave transmitter, slave receiver, and gc call. in a given application, i 2 c port may operate as a master or as a slave. in the slave mode, the i 2 c port hardware looks for its own slave address and the general call address. if one of these addresses is detected, and if the slave is willing to receive or transmit data from/to master(by setting the aa bit), acknowledge pulse will be transmitted out on the 9th clock, hence an interrupt is requested on both master and slave devices if interrupt is enabled. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible sl ave action didn?t be interrupted. if bus arbitration is lost in the master mode, i 2 c port switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 5.6.7.1 master transmitter mode serial data o utput through sda while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 0, and it is represented by ?w? in the flow diagrams. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. st art and stop conditions are output to indicate the beginning and the end of a serial transfer. 5.6.7.2 master receiver mode in this case the data direction bit (r/w) will be logic 1, and it is represented by ?r? in the flow diagrams. thus the first byte transmitted is sla+ r. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 5.6.7.3 slave receiver mode serial data a nd the serial clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 5.6.7.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via sda while the serial clock is input through scl. start and stop conditions are recognized as the beginning and end of a serial transfer. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 277 - revision v1.06 5.6.8 data transfer flow in five operating modes the five operating modes are: master/transmi tter, master/receiver, slave/transmitter, slave/receiver and gc call. bits sta, sto and aa in i2con register will determine the next state of the i 2 c hardware after si flag is cleared. upon completion of the new action, a new status code will be updated and the si flag will be set. if the i2 c interrupt control bit ei (i2con [7]) is set, appropriate action or software branch of the new status code can be performed in the interrupt service routine. data transfers in each mode are shown in the figure 5-26 to figure 5-31. figure 5-26 legend for the following five figures numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 278 - revision v1.06 figure 5-27 master transmitter mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 279 - revision v1.06 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,1,x) sla+r will be transmitted; ack bit will be received. set sta to generate a start. 40h sla+r has been transmitted; ack has been received. (sta,sto,si,aa)=(0,1,1,x) a stop will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,1,x) a stop followed by a start will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(0,0,1,0) data byte will be received; not ack will be returned. send a stop (sta,sto,si,aa)=(0,0,1,1) data byte will be received; ack will be returned. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,1,x) sla+r will be transmitted; ack bit will be transmitted; sio1 will be switched to mode. (sta,sto,si,aa)=(1,0,1,x) a start will be transmitted; when the bus becomes free (sta,sto,si,aa)=(0,0,1,x) i2c bus will be release; not address slv mode will be entered. enter naslave from master/transmitter (a) to master/transmitter (b) from slave mode (c) 48h sla+r has been transmitted; not ack has been received. 58h data byte has been received; not ack has been returned. 50h data byte has been received; ack has been returned. send a stop followed by a start 38h arbitration lost in not ack bit. send a start when bus becomes free (sta,sto,si,aa)=(1,0,1,x) a repeated start will be transmitted; figure 5-28 master receiver mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 280 - revision v1.06 figure 5-29 slave transmitter mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 281 - revision v1.06 set aa 60h own sla+w has been received; ack has been return. or 68h arbitration lost sla+r/w as master; own sla+w has been received; ack has been return. (sta,sto,si, aa)=(1,0,1,1) switch to not addressed slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,1,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,1,1) data will be received; ack will be returned. send a start when bus becomes free 88h previously addressed with own sla address; not ack has been returned. (sta,sto,si,aa)=(1,0,1,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,1,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,1,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(0,0,1,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,1,1) data byte will be received; ack will be returned. 80h previously addressed with own sla address; data has been received; ack has been returned. a0h a stop or repeated start has been received while still addressed as slv/rec. figure 5-30 slave receiver mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 282 - revision v1.06 figure 5-31 gc mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 283 - revision v1.06 5.7 pwm generator and capture timer (pwm) 5.7.1 overview numicro ? nuc100 medium density has 2 sets of pw m group supports total 4 sets of pwm generators which can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable dead-zone generators. numicro ? nuc100 low density only support 1 set of pwm group supports total 2 sets of pwm generators which can be configured as 4 independent pwm outputs, pwm0~pwm3, or as 2 complementary pwm pairs, (pwm0, pwm1) and (pwm2, pwm3) with 2 programmable dead-zone generators. each pwm generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16-bit pwm down- counters for pwm period control, two 16-bit comparators for pwm duty control and one dead- zone generator. the 4 sets of pwm generators provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one-shot mode to produce only one pwm cycle signal or auto-reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perf orm complementary pwm paired function; the paired pwm timing, period, duty and dead-time are determined by pwm0 timer and dead-zone generator 0. similarly, the complementary pw m pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead-zone generator 2, 4 and 6, respectively. refer to figure 5-32 to figure 5-39 for the architecture of pwm timers. to preve nt pwm driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching ze ro. the double buffering feature avoids glitch at pwm outputs. when the 16-bit period down counter reaches ze ro, the interrupt request is generated. if pwm- timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm-timer is set as one-shot mode, the down count er will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down-counter value matches the value of compare register. the alternate feature of the pwm-timer is digita l input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm 0; and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm-timer before ena ble capture feature. a fter capture feature is enabled, the capture always latched pwm-counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm-counter to capture falling latch register (cflr) when input channel has a fallin g transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ie0[1] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr0 and ccr2. for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this moment. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 284 - revision v1.06 the maximum captured frequency that pwm can c apture is confined by the capture interrupt latency. when capture interrupt occurred, softw are will do at least three steps, they are: read piirx to get interrupt source and read pwm_ crlx/pwm_cflx(x=0~3) to get capture value and finally write 1 to clear piirx to zero. if interrupt latency will take time t0 to finish, the capture signal mustn?t transition during this interval (t0). in this case, the maximum capture frequency will be 1/t0. for example: hclk = 50mhz, pwm_clk = 25mhz, interrupt latency is 900 ns so the maximum capture frequency will is 1/900ns 1000 khz 5.7.2 features 5.7.2.1 pwm function features: z pwm group has two pwm generators. each pwm generator supports one 8-bit prescaler, one clock divider, two pwm-timers (down counter), one dead-zone generator and two pwm outputs. z up to 16 bits resolution z pwm interrupt request synchronized with pwm period z one-shot or auto-reload mode pwm z up to 2 pwm group (pwma/pwmb) to support 8 pwm channels or 4 pwm paired channels (only 1 pwm group support for low density) 5.7.2.2 capture function features: z timing control logic shared with pwm generators z support 8 capture input channels shared with 8 pwm output channels (low density only support 4 capture input channels shared with 4 pwm output channels) z each channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 285 - revision v1.06 5.7.3 block diagram the figure 5-32 to figure 5-39 illustrate the architecture of pwm in pair (pwm-timer 0&1 are in one pai r and pwm-timer 2&3 are in another one, and so on.). figure 5-32 pwm generator 0 clock source control figure 5-33 pwm generator 0 architecture diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 286 - revision v1.06 figure 5-34 pwm generator 2 clock source control figure 5-35 pwm generator 2 architecture diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 287 - revision v1.06 figure 5-36 pwm generator 4 clock source control figure 5-37 pwm generator 4 architecture diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 288 - revision v1.06 figure 5-38 pwm generator 6 clock source control figure 5-39 pwm generator 6 architecture diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 289 - revision v1.06 5.7.4 function description 5.7.4.1 pwm-timer operation the pw m period and duty control are configured by pwm down-counter register (cnr) and pwm comparator register (cmr). the pwm-timer timing operation is shown in figure 5-41. the pulse widt h modulation follows the formula as below and the legend of pwm-timer comparator is shown as figure 5-40. note that the corresponding gpio pins must be configured as pwm function (ena ble poe and disable capenr) for the corresponding pwm channel. z pwm frequency = pwmxy_clk/(prescale+1)*(clock divider)/(cnr+1); where xy, could be 01, 23, 45 or 67, depends on selected pwm channel. z duty ratio = (cmr+1)/(cnr+1) z cmr >= cnr: pwm output is always high z cmr < cnr: pwm low width= (cnr-cmr) unit[1]; pwm high width = (cmr+1) unit z cmr = 0: pwm low width = (cnr) unit; pwm high width = 1 unit note: [1] unit = one pwm clock cycle. note: x= 0~3. figure 5-40 legend of internal co mparator output of pwm-timer numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 290 - revision v1.06 comparator (cmr) 1 0 pwm down-counter 33 2 1 0 4 3 2 1 0 4 pwm-timer output 1 cmr = 1 cnr = 3 auto reload = 1 (chxmod=1) set chxen=1 (pwm-timer starts running) cmr = 0 cnr = 4 auto-load (s/w write new value) auto-load (write initial setting) (h/w update value) (pwmifx is set by h/w) (pwmifx is set by h/w) figure 5-41 pwm-timer operation timing 5.7.4.2 pwm double buffering, auto-reload and one-shot operation pwm time rs have double buffering function the reload value is updated at the start of next period without affecting current timer operation. the pwm counter value can be written into cnrx and current pwm counter value can be read from pdrx. the bit ch0mod in pwm control register (pcr) defines pwm0 operates in auto-reload or one- shot mode if ch0mod is set to one, the auto-relo ad operation loads cnr0 to pwm counter when pwm counter reaches zero. if cnr0 are set to zero, pwm counter will be halt when pwm counter counts to zero. if ch0mod is set as zero, counter will be stopped immediately. pwm1~pwm7 performs the same function as pwm0. pwm waveform write a nonzero number to prescaler & setup clock dividor start write cnr=150 cmr=50 151 51 200 50 write cnr=199 cmr=49 write cnr=99 cmr=0 100 1 write cnr=0 cmr=xx stop figure 5-42 pwm double buffering illustration numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 291 - revision v1.06 5.7.4.3 modulate duty ratio the dou ble buffering function allows cmrx written at any point in current cycle. the loaded value will take effect from next cycle. modulate pwm controller ouput duty ratio (cnr = 150) write cmr=100 write cmr=50 write cmr=0 1 pwm cycle = 151 1 pwm cycle = 151 1 pwm cycle = 151 101 51 1 figure 5-43 pwm controller output duty ratio 5.7.4.4 dead-zone generator pwm co ntroller is implemented with dead zone generator. they are built for power device protection. this function generates a progra mmable time gap to delay pwm rising output. user can program pprx.dzi to determine the dead zone interval. figure 5-44 paired-pwm output with dead zone generation operation numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 292 - revision v1.06 5.7.4.5 capture operation the captu re 0 and pwm 0 share one timer that included in pwm 0; and the capture 1 and pwm 1 share another timer, and etc. the capture always latches pwm-counter to crlrx when input channel has a rising transition and latches pwm-counter to cflrx when input channel has a falling transition. capture channel 0 interrupt is programmable by setting ccr0[1] (rising latch interrupt enable) and ccr0[2] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feat ure by setting ccr0[17] and ccr0[18], and etc. whenever the capture controller issues a capture interrupt, the corresponding pwm counter will be reloaded with cnrx at this moment. note that the corresponding gpio pins must be configured as capture function (disable poe and enable capenr) for the corresponding capture channel. 8 7 6 5 4 3 2 1 8 7 6 5 pwm counter 17 capture input x cflrx 5 crlrx set by h/w clear by s/w capifx cfl_iex crl_iex capchxen set by h/w clear by s/w cflrix set by h/w clear by s/w note: x=0~3 crlrix reload reload (if cnrx = 8) no reload due to no capifx figure 5-45 capture operation timing at this case, the cnr is 8: 1. the pwm counter will be reloaded with cnrx when a capture inte rrupt flag (capifx) is set. 2. the channel low pulse width is (cnr + 1 - crlr). 3. the channel high pulse width is (cnr + 1 - cflr). 5.7.4.6 pwm-timer interrupt architecture there a re eight pwm interrupts, pwm0_int~pwm7_int, which are divided into pwma_int and numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 293 - revision v1.06 pwmb_int for advanced interrupt controller (aic). pwm 0 and capture 0 share one interrupt, pwm1 and capture 1 share the same interrupt and so on. therefore, pwm function and capture function in the same channel cannot be used at the same time. figure 5-46 demonstrates the architecture of pwm-timer interrupts. pwm0_int pwmif0 capif0 pwm1_int pwmif1 capif1 pwm2_int pwmif2 capif2 pwm3_int pwmif3 capif3 pwma_int figure 5-46 pwm group a pwm-timer interrupt architecture diagram figure 5-47 pwm group b pwm-timer interrupt architecture diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 294 - revision v1.06 5.7.4.7 pwm-timer start procedure the followi ng procedure is recommended for starting a pwm drive. 1. setup clock selector (csr) 2. setup prescaler (ppr) 3. setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and stop pwm-timer (pcr) 4. setup comparator register (cmr) for setting pwm duty. 5. setup pwm down-counter register (cnr) for setting pwm period. 6. setup interrupt enable register (pier) 7. setup corresponding gpio pins as pwm function (enable poe and disable capenr) for the corresponding pwm channel. 8. enable pwm timer start running (set chxen = 1 in pcr) 5.7.4.8 pwm-timer stop procedure method 1: set 16-bit down counter (cnr) as 0, and monitor pdr (current value of 16-bit down-counter). when pdr reaches to 0, disable pwm-timer (chxen in pcr). (recommended) method 2: set 16-bit down counter (cnr) as 0. when interrupt request happened, disable pwm-timer (chxen in pcr). (recommended) method 3: disable pwm-timer directly ((chxen in pcr). (not recommended) the reason why method 3 is not recommended is that disable chxen will immediately stop pwm output signal and lead to change the duty of the pwm output, this may cause damage to the control circuit of motor numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 295 - revision v1.06 5.7.4.9 capture start procedure 1. setup clock selector (csr) 2. setup prescaler (ppr) 3. setup channel enabled, rising/falling interrupt enable and input signal inverter on/off (ccr0, ccr1) 4. setup pwm down-counter (cnr) 5. setup corresponding gp io pins as capture function (disable poe and enable capenr) for the corresponding pwm channel. 6. enable pwm timer start running (set chxen = 1 in pcr) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 296 - revision v1.06 5.7.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value pwma_ba = 0x4004_0000 (pwm group a) pwmb_ba = 0x4014_0000 (pwm group b) (pwm group b only support in medium density) pwma_ba+0x00 r/w pwm group a prescaler register 0x0000_0000 ppr pwmb_ba+0x00 r/w pwm group b prescaler register (medium density only) 0x0000_0000 pwma_ba+0x04 r/w pwm group a clock select register 0x0000_0000 csr pwmb_ba+0x04 r/w pwm group b clock select register (medium density only) 0x0000_0000 pwma_ba+0x08 r/w pwm group a control register 0x0000_0000 pcr pwmb_ba+0x08 r/w pwm group b control register (medium density only) 0x0000_0000 pwma_ba+0x0c r/w pwm group a counter register 0 0x0000_0000 cnr0 pwmb_ba+0x0c r/w pwm group b counter register 0 (medium density only) 0x0000_0000 pwma_ba+0x10 r/w pwm group a comparator register 0 0x0000_0000 cmr0 pwmb_ba+0x10 r/w pwm group b comparator register 0 (medium density only) 0x0000_0000 pwma_ba+0x14 r pwm group a data register 0 0x0000_0000 pdr0 pwmb_ba+0x14 r pwm group b data register 0 (medium density only) 0x0000_0000 pwma_ba+0x18 r/w pwm group a counter register 1 0x0000_0000 cnr1 pwmb_ba+0x18 r/w pwm group b counter register 1 (medium density only) 0x0000_0000 pwma_ba+0x1c r/w pwm group a comparator register 1 0x0000_0000 cmr1 pwmb_ba+0x1c r/w pwm group b comparator register 1 (medium density only) 0x0000_0000 pwma_ba+0x20 r pwm group a data register 1 0x0000_0000 pdr1 pwmb_ba+0x20 r pwm group b data register 1 (medium density only) 0x0000_0000 cnr2 pwma_ba+0x24 r/w pwm group a counter register 2 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 297 - revision v1.06 pwmb_ba+0x24 r/w pwm group b counter register 2 (medium density only) 0x0000_0000 pwma_ba+0x28 r/w pwm group a comparator register 2 0x0000_0000 cmr2 pwmb_ba+0x28 r/w pwm group b comparator register 2 (medium density only) 0x0000_0000 pwma_ba+0x2c r pwm group a data register 2 0x0000_0000 pdr2 pwmb_ba+0x2c r pwm group b data register 2 (medium density only) 0x0000_0000 pwma_ba+0x30 r/w pwm group a counter register 3 0x0000_0000 cnr3 pwmb_ba+0x30 r/w pwm group b counter register 3 (medium density only) 0x0000_0000 pwma_ba+0x34 r/w pwm group a comparator register 3 0x0000_0000 cmr3 pwmb_ba+0x34 r/w pwm group b comparator register 3 (medium density only) 0x0000_0000 pwma_ba+0x38 r pwm group a data register 3 0x0000_0000 pdr3 pwmb_ba+0x38 r pwm group b data register 3 (medium density only) 0x0000_0000 pbcr pwma_ba+0x3c r/w pwm backward compatible register (low density only) 0x0000_0000 pwma_ba+0x40 r/w pwm group a interrupt enable register 0x0000_0000 pier pwmb_ba+0x40 r/w pwm group b interrupt enable register (medium density only) 0x0000_0000 pwma_ba+0x44 r/c pwm group a interrupt indication register 0x0000_0000 piir pwmb_ba+0x44 r/c pwm group b interrupt indication register (medium density only) 0x0000_0000 pwma_ba+0x50 r/w pwm group a capture control register 0 0x0000_0000 ccr0 pwmb_ba+0x50 r/w pwm group b capture control register 0 (medium density only) 0x0000_0000 pwma_ba+0x54 r/w pwm group a capture control register 2 0x0000_0000 ccr2 pwmb_ba+0x54 r/w pwm group b capture control register 2 (medium density only) 0x0000_0000 pwma_ba+0x58 r pwm group a capture risi ng latch register (channel 0) 0x0000_0000 crlr0 pwmb_ba+0x58 r pwm group b capture rising latch register (channel 0) (medium density only) 0x0000_0000 cflr0 pwma_ba+0x5c r pwm group a capture falling latch register (channel 0) 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 298 - revision v1.06 pwmb_ba+0x5c r pwm group b capture falling latch register (channel 0) (medium density only) 0x0000_0000 pwma_ba+0x60 r pwm group a capture risi ng latch register (channel 1) 0x0000_0000 crlr1 pwmb_ba+0x60 r pwm group b capture rising latch register (channel 1) (medium density only) 0x0000_0000 pwma_ba+0x64 r pwm group a capture falling latch register (channel 1) 0x0000_0000 cflr1 pwmb_ba+0x64 r pwm group b capture falling latch register (channel 1) (medium density only) 0x0000_0000 pwma_ba+0x68 r pwm group a capture risi ng latch register (channel 2) 0x0000_0000 crlr2 pwmb_ba+0x68 r pwm group b capture rising latch register (channel 2) (medium density only) 0x0000_0000 pwma_ba+0x6c r pwm group a capture falling latch register (channel 2) 0x0000_0000 cflr2 pwmb_ba+0x6c r pwm group b capture falling latch register (channel 2) (medium density only) 0x0000_0000 pwma_ba+0x70 r pwm group a capture risi ng latch register (channel 3) 0x0000_0000 crlr3 pwmb_ba+0x70 r pwm group b capture rising latch register (channel 3) (medium density only) 0x0000_0000 pwma_ba+0x74 r pwm group a capture falling latch register (channel 3) 0x0000_0000 cflr3 pwmb_ba+0x74 r pwm group b capture falling latch register (channel 3) (medium density only) 0x0000_0000 pwma_ba+0x78 r/w pwm group a capture input 0~3 enable register 0x0000_0000 capenr pwmb_ba+0x78 r/w pwm group b capture input 0~3 enable register (medium density only) 0x0000_0000 pwma_ba+0x7c r/w pwm group a out put enable for channel 0~3 0x0000_0000 poe pwmb_ba+0x7c r/w pwm group b output enable for channel 0~3 (medium density only) 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 299 - revision v1.06 5.7.6 register description pwm pre-scale register (ppr) register offset r/w description reset value pwma_ba+0x00 r/w pwm group a pre-scale register 0x0000_0000 ppr pwmb_ba+0x00 r/w pwm group b pre-scale register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 dzi23 23 22 21 20 19 18 17 16 dzi01 15 14 13 12 11 10 9 8 cp23 7 6 5 4 3 2 1 0 cp01 bits descriptions [31:24] dzi23 dead zone interval for pair of channel2 and channel3 (pwm2 and pwm3 pair for pwm group a, pwm6 and pwm7 pair for pwm group b) these 8 bits determine dead zone length. the unit time of dead zone length is received from corresponding csr bits. [23:16] dzi01 dead zone interval for pair of channel 0 and channel 1 (pwm0 and pwm1 pair for pwm group a, pwm4 and pwm5 pair for pwm group b) these 8 bits determine dead zone length. the unit time of dead zone length is received from corresponding csr bits. [15:8] cp23 clock prescaler 2 (pwm-timer2 & 3 for group a and pwm-timer 6 & 7 for group b) clock input is divided by (cp23 + 1) before it is fed to the corresponding pwm-timer if cp23=0, then the clock prescaler 2 output clock will be stopped. so corresponding pwm-timer will be stopped also. [7:0] cp01 clock prescaler 0 (pwm-timer 0 & 1 for group a and pwm-timer 4 & 5 for group b) clock input is divided by (cp01 + 1) before it is fed to the corresponding pwm-timerr if cp01=0, then the clock prescaler 0 output clock will be stopped. so corresponding pwm-timer will be stopped also. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 300 - revision v1.06 pwm clock selector register (csr) register offset r/w description reset value pwma_ba+0x04 r/w pwm group a cl ock selector register 0x0000_0000 csr pwmb_ba+0x04 r/w pwm group b clock selector register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved csr3 reserved csr2 7 6 5 4 3 2 1 0 reserved csr1 reserved csr0 bits descriptions [31:15] reserved reserved [14:12] csr3 pwm timer 3 clock source selection (pwm timer 3 for group a and pwm timer 7 for group b) select clock input for pwm timer. csr3 [14:12] input clock divided by 100 1 011 16 010 8 001 4 000 2 [11] reserved reserved [10:8] csr2 pwm timer 2 clock source selection (pwm timer 2 for group a and pwm timer 6 for group b) select clock input for pwm timer. (table is the same as csr3) [7] reserved reserved [6:4] csr1 pwm timer 1 clock source selection (pwm timer 1 for group a and pwm timer 5 for group b) select clock input for pwm timer. (table is the same as csr3) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 301 - revision v1.06 [3] reserved reserved [2:0] csr0 pwm timer 0 clock source selection (pwm timer 0 for group a and pwm timer 4 for group b) select clock input for pwm timer. (table is the same as csr3) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 302 - revision v1.06 pwm control register (pcr) register offset r/w description reset value pwma_ba+0x08 r/w pwm group a control register (pcr) 0x0000_0000 pcr pwmb_ba+0x08 r/w pwm group b control register (pcr) (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved ch3mod ch3inv reserved ch3en 23 22 21 20 19 18 17 16 reserved ch2mod ch2inv reserved ch2en 15 14 13 12 11 10 9 8 reserved ch1mod ch1inv reserved ch1en 7 6 5 4 3 2 1 0 reserved dzen23 dzen01 ch0mod ch0inv reserved ch0en bits descriptions [31:28] reserved reserved [27] ch3mod pwm-timer 3 auto-reload/one-shot mode (pwm timer 3 for group a and pwm timer 7 for group b) 1 = auto-reload mode 0 = one-shot mode note: if there is a rising transition at this bit, it will cause cnr3 and cmr3 be clear. [26] ch3inv pwm-timer 3 output inverter enable (pwm timer 3 for group a and pwm timer 7 for group b) 1 = inverter enable 0 = inverter disable [25] reserved reserved [24] ch3en pwm-timer 3 enable (pwm timer 3 for group a and pwm timer 7 for group b) 1 = enable corresponding pwm-timer start run 0 = stop corresponding pwm-timer running [23:20] reserved reserved [19] ch2mod pwm-timer 2 auto-reload/one-shot mode (pwm timer 2 for group a and pwm timer 6 for group b) 1 = auto-reload mode 0 = one-shot mode note: if there is a rising transition at this bit, it will cause cnr2 and cmr2 be clear. [18] ch2inv pwm-timer 2 output inverter enable (pwm timer 2 for group a and pwm timer 6 for numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 303 - revision v1.06 group b) 1 = inverter enable 0 = inverter disable [17] reserved reserved [16] ch2en pwm-timer 2 enable (pwm timer 2 for group a and pwm timer 6 for group b) 1 = enable corresponding pwm-timer start run 0 = stop corresponding pwm-timer running [15:12] reserved reserved [11] ch1mod pwm-timer 1 auto-reload/one-shot mode (pwm timer 1 for group a and pwm timer 5 for group b) 1 = auto-load mode 0 = one-shot mode note: if there is a rising transition at this bit, it will cause cnr1 and cmr1 be clear. [10] ch1inv pwm-timer 1 output inverter enable (pwm timer 1 for group a and pwm timer 5 for group b) 1 = inverter enable 0 = inverter disable [9] reserved reserved [8] ch1en pwm-timer 1 enable (pwm timer 1 for group a and pwm timer 5 for group b) 1 = enable corresponding pwm-timer start run 0 = stop corresponding pwm-timer running [7:6] reserved reserved [5] dzen23 dead-zone 2 generator enable (pwm2 and pwm3 pair for pwm group a, pwm6 and pwm7 pair for pwm group b) 1 = enable 0 = disable note: when dead-zone generator is enabled, the pair of pwm2 and pwm3 becomes a complementary pair for pwm group a and the pair of pwm6 and pwm7 becomes a complementary pair for pwm group b. [4] dzen01 dead-zone 0 generator enable (pwm0 and pwm1 pair for pwm group a, pwm4 and pwm5 pair for pwm group b) 1 = enable 0 = disable note: when dead-zone generator is enabled, the pair of pwm0 and pwm1 becomes a complementary pair for pwm group a and the pair of pwm4 and pwm5 becomes a complementary pair for pwm group b. [3] ch0mod pwm-timer 0 auto-reload/one-shot mode (pwm timer 0 for group a and pwm timer 4 for group b) 1 = auto-reload mode 0 = one-shot mode note: if there is a rising transition at this bit, it will cause cnr0 and cmr0 be clear. [2] ch0inv pwm-timer 0 output inverter enable (pwm timer 0 for group a and pwm timer 4 for group b) 1 = inverter enable numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 304 - revision v1.06 0 = inverter disable [1] reserved reserved [0] ch0en pwm-timer 0 enable (pwm timer 0 for group a and pwm timer 4 for group b) 1 = enable corresponding pwm-timer start run 0 = stop corresponding pwm-timer running numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 305 - revision v1.06 pwm counter register 3-0 (cnr3-0) register offset r/w description reset value pwma_ba+0x0c r/w pwm group a counter register 0 0x0000_0000 cnr0 pwmb_ba+0x0c r/w pwm group b counter register 0 (medium density only) 0x0000_0000 pwma_ba+0x18 r/w pwm group a counter register 1 0x0000_0000 cnr1 pwmb_ba+0x18 r/w pwm group b counter register 1 (medium density only) 0x0000_0000 pwma_ba+0x24 r/w pwm group a counter register 2 0x0000_0000 cnr2 pwmb_ba+0x24 r/w pwm group b counter register 2 (medium density only) 0x0000_0000 pwma_ba+0x30 r/w pwm group a counter register 3 0x0000_0000 cnr3 pwmb_ba+0x30 r/w pwm group b counter register 3 (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cnrx [15:8] 7 6 5 4 3 2 1 0 cnrx [7:0] bits descriptions [31:16] reserved reserved [15:0] cnrx pwm timer loaded value cnr determines the pwm period. z pwm frequency = pwmxy_clk/(prescale+1)*(clock divider)/(cnr+1); where xy, could be 01, 23, 45 or 67, depends on selected pwm channel. z duty ratio = (cmr+1)/(cnr+1). z cmr >= cnr: pwm output is always high. z cmr < cnr: pwm low width = (cnr-cmr) unit; pwm high width = (cmr+1) unit. z cmr = 0: pwm low width = (cnr) unit; pwm high width = 1 unit (unit = one pwm clock cycle) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 306 - revision v1.06 note: any write to cnr will take effect in next pwm cycle. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 307 - revision v1.06 pwm comparator register 3-0 (cmr3-0) register offset r/w description reset value pwma_ba+0x10 r/w pwm group a comparator register 0 0x0000_0000 cmr0 pwmb_ba+0x10 r/w pwm group b comparator register 0 (medium density only) 0x0000_0000 pwma_ba+0x1c r/w pwm group a comparator register 1 0x0000_0000 cmr1 pwmb_ba+0x1c r/w pwm group b comparator register 1 (medium density only) 0x0000_0000 pwma_ba+0x28 r/w pwm group a comparator register 2 0x0000_0000 cmr2 pwmb_ba+0x28 r/w pwm group b comparator register 2 (medium density only) 0x0000_0000 pwma_ba+0x34 r/w pwm group a comparator register 3 0x0000_0000 cmr3 pwmb_ba+0x34 r/w pwm group b comparator register 3 (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cmrx [15:8] 7 6 5 4 3 2 1 0 cmrx [7:0] bits descriptions [31:16] reserved reserved [15:0] cmrx pwm comparator register cmr determines the pwm duty. z pwm frequency = pwmxy_clk/(prescale+1)*(clock divider)/(cnr+1); where xy, could be 01, 23, 45 or 67, depends on selected pwm channel. z duty ratio = (cmr+1)/(cnr+1). z cmr >= cnr: pwm output is always high. z cmr < cnr: pwm low width = (cnr-cmr) unit; pwm high width = (cmr+1) unit. z cmr = 0: pwm low width = (cnr) unit; pwm high width = 1 unit (unit = one pwm clock cycle) note: any write to cmr will take effect in next pwm cycle. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 308 - revision v1.06 pwm data register 3-0 (pdr 3-0) register offset r/w description reset value pwma_ba0+0x14 r pwm group a data register 0 0x0000_0000 pdr0 pwmb_ba0+0x14 r pwm group b data register 0 (medium density only) 0x0000_0000 pwma_ba0+0x20 r pwm group a data register 1 0x0000_0000 pdr1 pwmb_ba0+0x20 r pwm group b data register 1 (medium density only) 0x0000_0000 pwma_ba0+0x2c r pwm group a data register 2 0x0000_0000 pdr2 pwmb_ba0+0x2c r pwm group b data register 2 (medium density only) 0x0000_0000 pwma_ba0+0x38 r pwm group a data register 3 0x0000_0000 pdr3 pwmb_ba0+0x38 r pwm group b data register 3 (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 pdr[15:8] 7 6 5 4 3 2 1 0 pdr[7:0] bits descriptions [31:16] reserved reserved [15:0] pdrx pwm data register user can monitor pdr to know the current value in 16-bit down counter. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 309 - revision v1.06 pwm backward compatible register (this bit only support in low density) register offset r/w description reset value pbcr pwm_ba0+0x3c r/w pwm backward compatible register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bcn bits descriptions [31:1] reserved reserved [0] bcn pwm backward compatible register 0 = pwm register action is compatible with medium density 1 = pwm register action is not compatible with medium density please reference ccr0/ccr2 register bit 6, 7, 22, 23 description numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 310 - revision v1.06 pwm interrupt enable register (pier) register offset r/w description reset value pwma_ba+0x40 r/w pwm group a interrupt enable register 0x0000_0000 pier pwmb_ba+0x40 r/w pwm group b interrupt enable register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pwmie3 pwmie2 pwmie1 pwmie0 bits descriptions [31:4] reserved reserved [3] pwmie3 pwm channel 3 interrupt enable 1 = enable 0 = disable [2] pwmie2 pwm channel 2 interrupt enable 1 = enable 0 = disable [1] pwmie1 pwm channel 1 interrupt enable 1 = enable 0 = disable [0] pwmie0 pwm channel 0 interrupt enable 1 = enable 0 = disable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 311 - revision v1.06 pwm interrupt indication register (piir) register offset r/w description reset value pwma_ba+0x44 r/w pwm group a inte rrupt indication register 0x0000_0000 piir pwmb_ba+0x44 r/w pwm group b interrupt indication register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pwmif3 pwmif2 pwmif1 pwmif0 bits descriptions [31:4] reserved reserved [3] pwmif3 pwm channel 3 interrupt status flag is set by hardware when pwm3 down counter reaches zero, software can write 1 to clear this bit to zero [2] pwmif2 pwm channel 2 interrupt status flag is set by hardware when pwm2 down counter reaches zero, software can write 1 to clear this bit to zero [1] pwmif1 pwm channel 1 interrupt status flag is set by hardware when pwm1 down counter reaches zero, software can write 1 to clear this bit to zero [0] pwmif0 pwm channel 0 interrupt status flag is set by hardware when pwm0 down counter reaches zero, software can write 1 to clear this bit to zero note: user can clear each interrupt flag by writing 1 to corresponding bit in piir. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 312 - revision v1.06 capture control register (ccr0) register offset r/w description reset value pwma_ba+0x50 r/w pwm group a capture control register 0x0000_0000 ccr0 pwmb_ba+0x50 r/w pwm group b capture control register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 cflri1 crlri1 reserved capif1 capch1en fl_ie1 rl_ie1 inv1 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 cflri0 crlri0 reserved capif0 capch0en fl_ie0 rl_ie0 inv0 bits descriptions [31:24] reserved reserved [23] cflri1 cflr1 latched indicator bit when pwm group input channel 1 has a falling transition, cflr1 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [22] crlri1 crlr1 latched indicator bit when pwm group input channel 1 has a rising transition, crlr1 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [5] reserved reserved [20] capif1 channel 1 capture interrupt indication flag if pwm group channel 1 rising latch inte rrupt is enabled (crl_ie1=1), a rising transition occurs at pwm group channel 1 will re sult in capif1 to high; similarly, a falling transition will cause capif1 to be set high if pwm group channel 1 falling latch interrupt is enabled (cfl_ie1=1). write 1 to clear this bit to zero [19] capch1en channel 1 capture function enable 1 = enable capture function on pwm group channel 1 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 313 - revision v1.06 0 = disable capture func tion on pwm group channel 1 when enable, capture latched the pwm-count er and saved to crlr (rising latch) and cflr (falling latch). when disable, capture does not update cr lr and cflr, and disable pwm group channel 1 interrupt. [18] fl_ie1 channel 1 falling latch interrupt enable 1 = enable falling latch interrupt 0 = disable falling latch interrupt when enable, if capture detects pwm group channel 1 has falling transition, capture issues an interrupt. [17] rl_ie1 channel 1 rising latch interrupt enable 1 = enable rising latch interrupt 0 = disable rising latch interrupt when enable, if capture detects pwm group channel 1 has rising transition, capture issues an interrupt. [16] inv1 channel 1 inverter enable 1 = inverter enable. reverse the input signal from gpio before fed to capture timer 0 = inverter disable [15:8] reserved reserved [7] cflri0 cflr0 latched indicator bit when pwm group input channel 0 has a falling transition, cflr0 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [6] crlri0 crlr0 latched indicator bit when pwm group input channel 0 has a rising transition, crlr0 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [5] reserved reserved [4] capif0 channel 0 capture interrupt indication flag if pwm group channel 0 rising latch inte rrupt is enabled (crl_ie0=1), a rising transition occurs at pwm group channel 0 will re sult in capif0 to high; similarly, a falling transition will cause capif0 to be set high if pwm group channel 0 falling latch interrupt is enabled (cfl_ie0=1). write 1 to clear this bit to zero [3] capch0en channel 0 capture function enable 1 = enable capture function on pwm group channel 0. 0 = disable capture func tion on pwm group channel 0 when enable, capture latched the pwm-counter value and saved to crlr (rising latch) and cflr (falling latch). when disable, capture does not update cr lr and cflr, and disable pwm group channel 0 interrupt. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 314 - revision v1.06 [2] fl_ie0 channel 0 falling latch interrupt enable 1 = enable falling latch interrupt 0 = disable falling latch interrupt when enable, if capture detects pwm group channel 0 has falling transition, capture issues an interrupt. [1] rl_ie0 channel 0 rising latch interrupt enable 1 = enable rising latch interrupt 0 = disable rising latch interrupt when enable, if capture detects pwm group channel 0 has rising transition, capture issues an interrupt. [0] inv0 channel 0 inverter enable 1 = inverter enable. reverse the input signal from gpio before fed to capture timer 0 = inverter disable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 315 - revision v1.06 capture control register (ccr2) register offset r/w description reset value pwma_ba+0x54 r/w pwm group a capture control register 0x0000_0000 ccr2 pwmb_ba+0x54 r/w pwm group b capture control register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 cflri3 crlri3 reserved capif3 capch3en fl_ie3 rl_ie3 inv3 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 cflri2 crlri2 reserved capif2 capch2en fl_ie2 rl_ie2 inv2 bits descriptions [31:24] reserved reserved [23] cflri3 cflr3 latched indicator bit when pwm group input channel 3 has a falling transition, cflr3 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [22] crlri3 crlr3 latched indicator bit when pwm group input channel 3 has a rising transition, crlr3 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [21] reserved reserved [20] capif3 channel 3 capture interrupt indication flag if pwm group channel 3 rising latch inte rrupt is enabled (crl_ie3=1), a rising transition occurs at pwm group channel 3 will re sult in capif3 to high; similarly, a falling transition will cause capif3 to be set high if pwm group channel 3 falling latch interrupt is enabled (cfl_ie3=1). write 1 to clear this bit to zero [19] capch3en channel 3 capture function enable 1 = enable capture function on pwm group channel 3 0 = disable capture func tion on pwm group channel 3 when enable, capture latched the pwm-count er and saved to crlr (rising latch) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 316 - revision v1.06 and cflr (falling latch). when disable, capture does not update cr lr and cflr, and disable pwm group channel 3 interrupt. [18] cfl_ie3 channel 3 falling latch interrupt enable 1 = enable falling latch interrupt 0 = disable falling latch interrupt when enable, if capture detects pwm group channel 3 has falling transition, capture issues an interrupt. [17] crl_ie3 channel 3 rising latch interrupt enable 1 = enable rising latch interrupt 0 = disable rising latch interrupt when enable, if capture detects pwm group channel 3 has rising transition, capture issues an interrupt. [16] inv3 channel 3 inverter enable 1 = inverter enable. reverse the input signal from gpio before fed to capture timer 0 = inverter disable [15:8] reserved reserved [7] cflri2 cflr2 latched indicator bit when pwm group input channel 2 has a falling transition, cflr2 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [6] crlri2 crlr2 latched indicator bit when pwm group input channel 2 has a rising transition, crlr2 was latched with the value of pwm down-counter and this bit is set by hardware. in medium density, software can write 0 to clear this bit to zero. in low density, software can write 0 to clear this bit to zero if bcn bit is 0, and can write 1 to clear this bit to zero if bcn bit is 1. [5] reserved reserved [4] capif2 channel 2 capture interrupt indication flag if pwm group channel 2 rising latch inte rrupt is enabled (crl_ie2=1), a rising transition occurs at pwm group channel 2 will re sult in capif2 to high; similarly, a falling transition will cause capif2 to be set high if pwm group channel 2 falling latch interrupt is enabled (cfl_ie2=1). write 1 to clear this bit to zero [3] capch2en channel 2 capture function enable 1 = enable capture function on pwm group channel 2 0 = disable capture func tion on pwm group channel 2 when enable, capture latched the pwm-counter value and saved to crlr (rising latch) and cflr (falling latch). when disable, capture does not update cr lr and cflr, and disable pwm group channel 2 interrupt. [2] cfl_ie2 channel 2 falling latch interrupt enable 1 = enable falling latch interrupt numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 317 - revision v1.06 0 = disable falling latch interrupt when enable, if capture detects pwm group channel 2 has falling transition, capture issues an interrupt. [1] crl_ie2 channel 2 rising latch interrupt enable 1 = enable rising latch interrupt 0 = disable rising latch interrupt when enable, if capture detects pwm group channel 2 has rising transition, capture issues an interrupt. [0] inv2 channel 2 inverter enable 1 = inverter enable. reverse the input signal from gpio before fed to capture timer 0 = inverter disable numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 318 - revision v1.06 capture rising latch register3-0 (crlr3-0) register offset r/w description reset value pwma_ba+0x58 r pwm group a capture risi ng latch register (channel 0) 0x0000_0000 crlr0 pwmb_ba+0x58 r pwm group b capture rising latch register (channel 0) (medium density only) 0x0000_0000 pwma_ba+0x60 r pwm group a capture risi ng latch register (channel 1) 0x0000_0000 crlr1 pwmb_ba+0x60 r pwm group b capture rising latch register (channel 1) (medium density only) 0x0000_0000 pwma_ba+0x68 r pwm group a capture risi ng latch register (channel 2) 0x0000_0000 crlr2 pwmb_ba+0x68 r pwm group b capture rising latch register (channel 2) (medium density only) 0x0000_0000 pwma_ba+0x70 r pwm group a capture risi ng latch register (channel 3) 0x0000_0000 crlr3 pwmb_ba+0x70 r pwm group b capture rising latch register (channel 3) (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 crlrx [15:8] 7 6 5 4 3 2 1 0 crlrx [7:0] bits descriptions [31:16] reserved reserved [15:0] crlrx capture rising latch register latch the pwm counter when channel 0/1/2/3 has rising transition. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 319 - revision v1.06 capture falling latch register3-0 (cflr3-0) register offset r/w description reset value pwma_ba+0x5c r pwm group a capture falling latch register (channel 0) 0x0000_0000 cflr0 pwmb_ba+0x5c r pwm group b capture falling latch register (channel 0) (medium density only) 0x0000_0000 pwma_ba+0x64 r pwm group a capture falling latch register (channel 1) 0x0000_0000 cflr1 pwmb_ba+0x64 r pwm group b capture falling latch register (channel 1) (medium density only) 0x0000_0000 pwma_ba+0x6c r pwm group a capture falling latch register (channel 2) 0x0000_0000 cflr2 pwmb_ba+0x6c r pwm group b capture falling latch register (channel 2) (medium density only) 0x0000_0000 pwma_ba+0x74 r pwm group a capture falling latch register (channel 3) 0x0000_0000 cflr3 pwmb_ba+0x74 r pwm group b capture falling latch register (channel 3) (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cflrx [15:8] 7 6 5 4 3 2 1 0 cflrx [7:0] bits descriptions [31:16] reserved reserved [15:0] cflrx capture falling latch register latch the pwm counter when channel 01/2/3 has falling transition. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 320 - revision v1.06 capture input enable register (capenr) register offset r/w description reset value pwma_ba+0x78 r/w pwm group a capture input 0~3 enable register 0x0000_0000 capenr pwmb_ba+0x78 r/w pwm group b capture input 0~3 enable register (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved capenr bits descriptions [3:0] capenr capture input enable register there are four capture inputs from pad. bit0 ~bit3 are used to control each input enable or disable. 0 = disable (pwmx multi-func tion pin input does not affe ct input capture function.) 1 = enable (pwmx multi-function pin input will affect its input capture function.) capenr bit 3210 for pwm group a bit xxx1 ? capture channel 0 is from pin pa.12 bit xx1x ? capture channel 1 is from pin pa.13 bit x1xx ? capture channel 2 is from pin pa.14 bit 1xxx ? capture channel 3 is from pin pa.15 bit 3210 for pwm group b bit xxx1 ? capture channel 0 is from pin pe.11 bit xx1x ? capture channel 1 is from pin pe.5 bit x1xx ? capture channel 2 is from pin pe.0 bit 1xxx ? capture channel 3 is from pin pe.1 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 321 - revision v1.06 pwm output enable register (poe) register offset r/w description reset value pwma_ba+0x7c r/w pwm group a output enable register for channel 0~3 0x0000_0000 poe pwmb_ba+0x7c r/w pwm group b output enable register for channel 0~3 (medium density only) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pwm3 pwm2 pwm1 pwm0 bits descriptions [3] pwm3 channel 3 output enable register 1 = enable pwm channel 3 output to pin 0 = disable pwm channel 3 output to pin note: the corresponding gpio pin also must be switched to pwm function [2] pwm2 channel 2 output enable register 1 = enable pwm channel 2 output to pin 0 = disable pwm channel 2 output to pin note: the corresponding gpio pin also must be switched to pwm function [1] pwm1 channel 1 output enable register 1 = enable pwm channel 1 output to pin 0 = disable pwm channel 1 output to pin note: the corresponding gpio pin also must be switched to pwm function [0] pwm0 channel 0 output enable register 1 = enable pwm channel 0 output to pin 0 = disable pwm channel 0 output to pin note: the corresponding gpio pin also must be switched to pwm function numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 322 - revision v1.06 5.8 real time clock (rtc) 5.8.1 overview real time clock (rtc) controller provides user the real time and calendar message. the clock source of rtc is from an external 32.768 khz crystal connected at pins x32i and x32o (reference to pin descriptions) or from an external 32.768 khz oscillator output fed at pin x32i. the rtc controller provides the time message (s econd, minute, hour) in time loading register (tlr) as well as calendar message (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. it also offers alarm function that user can preset the alarm time in time alarm register (tar) and alarm calendar in calendar alarm register (car). the rtc controller supports periodic time tick and alarm match interrupts. the periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is equal to alarm setting time registers tar and car, the alarm interrupt flag (riir.aif) is set and the alarm interrupt is requested if the alarm interrupt is enabled (rier.aier=1). the rtc time tick if wakeup cpu function is enabled (twke (ttr[3])=1) and alarm match can cause cpu wakeup from sleep or power-down mode. 5.8.2 features z there is a time counter (second, minute, hou r) and calendar counter (day, month, year) for user to check the time z alarm register (second, minute, hour, day, month, year) z 12-hour or 24-hour mode is selectable z leap year compensation automatically z day of week counter z frequency compensate register (fcr) z all time and calendar message is expressed in bcd code z support periodic time tick interrupt with 8 peri od options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second z support rtc time tick and alarm match interrupt z support wake up cpu from sleep or power-down mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 323 - revision v1.06 5.8.3 block diagram the block diagram of real time clock is depicted as following: figure 5-48 rtc block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 324 - revision v1.06 5.8.4 function description 5.8.4.1 access to rtc register due to clo ck difference between rtc clock and system clock, when user write new data to any one of the registers, the register will not be updated until 2 rtc clocks later (60us). in addition, user must be aware that rtc contro ller does not check whether loaded data is out of bounds or not. rtc does not check rationality between dwr and clr either. 5.8.4.2 rtc initiation whe n rtc controller is power on, user has to write a number (0xa5eb1357) to inir to reset all logic. inir acts as hardware reset circuit. on ce inir has been set as 0xa5eb1357, there is no action for rtc if any value is programmed into inir register. 5.8.4.3 rtc read/write enable regi ster aer bit 15~0 is served as rtc read/write password to protect rtc registers. aer bit 15~0 has to be set as 0xa965 to enable access restriction. once it is set, it will take effect 512 rtc clocks later (about 15ms). programmer can read rtc enabled status flag in aer.enf to check whether if rtc controller start operating or not. 5.8.4.4 frequency compensation the rtc fcr allows software to make digital compensation to a clock input. the frequency of clock input must be in the range from 32776hz to 32761hz. user can utilize a frequency counter to measure rtc clock on one of gpio pin during manufacture, and store the value in flash memory for retrieval when the product is first power on. following are the compensation examples for higher or lower frequency clock input. example 1: frequency counter measurem ent : 32773.65hz ( > 32768 hz) integer part: 32773 => 0x8005 fcr.integer = 0x05 ? 0x01 + 0x08 = 0x0c fraction part: 0.65 x 60 = 39 => 0x27 fcr.fraction = 0x27 example 2 frequency counter measurement : 32765.27hz ( 32768 hz) Q integer part: 32765 => 0x7ffd fcr.integer = 0x0a ? 0x01 ? 0x08 = 0x04 fraction part: 0.27 x 60 = 16.2=> 0x10 fcr.fraction = 0x10 5.8.4.5 time and calendar counter tlr a nd clr are used to load the time and calendar. tar and car are used for alarm. they are all represented by bcd. 5.8.4.6 12/24 hour time scale selection the 12/24 h our time scale selection depends on tssr bit 0. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 325 - revision v1.06 5.8.4.7 day of the week counter the rt c controller provides day of week in da y of the week register (dwr). the value is defined from 0 to 6 to represent sunday to saturday respectively. 5.8.4.8 periodic time tick interrupt the pe riodic interrupt has 8 period option 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr.ttr[2:0]. when periodic time tick interrupt is enabled by setting rier.tier to 1, the periodic time tick interrupt is requested periodically in the period selected by ttr register. 5.8.4.9 alarm interrupt whe n rtc counter in tlr and clr is equal to alarm setting time tar and car the alarm interrupt flag (riir.aif) is set and the alarm interrupt is requested if the alarm interrupt is enabled (rier.aier=1). 5.8.4.10 application note: 1. tar, car, tlr and clr r egisters are all bcd counter. 2. programmer has to make sure that the l oaded values are reasonable. for example, load clr as 201a (year), 13 (month), 00 (day), or clr does not match with dwr, etc. 3. reset state : register reset state aer 0 clr 05/1/1 (year/month/day) tlr 00:00:00 (hour : minute : second) car 00/00/00 (year/month/day) tar 00:00:00 (hour : minute : second) tssr 1 (24 hr mode) dwr 6 (saturday) rier 0 riir 0 lir 0 ttr 0 4. in tlr and tar, only 2 bcd digits are used to express ?year?. we assume 2 bcd digits of xy denote 20xy, but not 19xy or 21xy. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 326 - revision v1.06 5.8.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value rtc_ba = 0x4000_8000 inir rtc_ba+0x00 r/w rtc initiation register 0x0000_0000 aer rtc_ba+0x04 r/w rtc access enable register 0x0000_0000 fcr rtc_ba+0x08 r/w rtc frequency compensation register 0x0000_0700 tlr rtc_ba+0x0c r/w time loading register 0x0000_0000 clr rtc_ba+0x10 r/w calendar loading register 0x0005_0101 tssr rtc_ba+0x14 r/w time scale selection register 0x0000_0001 dwr rtc_ba+0x18 r/w day of the week register 0x0000_0006 tar rtc_ba+0x1c r/w time alarm register 0x0000_0000 car rtc_ba+0x20 r/w calendar alarm register 0x0000_0000 lir rtc_ba+0x24 r leap year indicator register 0x0000_0000 rier rtc_ba+0x28 r/w rtc interrupt enable register 0x0000_0000 riir rtc_ba+0x2c r/c rtc interrupt indicator register 0x0000_0000 ttr rtc_ba+0x30 r/w rtc time tick register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 327 - revision v1.06 5.8.6 register description rtc initiation register (inir) register offset r/w description reset value inir rtc_ba+0x00 r/w rtc initiation register 0x0000_0000 31 30 29 28 27 26 25 24 inir 23 22 21 20 19 18 17 16 inir 15 14 13 12 11 10 9 8 inir 7 6 5 4 3 2 1 0 inir inir/active bits descriptions [31:0] inir rtc initiation when chip is power on, rtc timer counter is at unknown state because rtc timer counter reset is individual with chip reset; user has to write a number (0xa5eb1357) to inir to reset rtc controller to initialize rtc controller. [0] active rtc active status (read only) 0 = rtc is at reset state 1 = rtc is at normal active state. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 328 - revision v1.06 rtc access enable register (aer) register offset r/w description reset value aer rtc_ba+0x04 r/w rtc access enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved enf 15 14 13 12 11 10 9 8 aer 7 6 5 4 3 2 1 0 aer bits descriptions [31:17] reserved reserved [16] enf rtc register access enable flag (read only) 1 = rtc register read/write enable 0 = rtc register read/write disable this bit will be set after aer[15:0] register is load a 0xa965, and be clear automatically 512 rtc clock or aer[15:0] is not 0xa965. register aer.enf 1 0 inir r/w r/w aer r/w r/w fcr r/w - tlr r/w r clr r/w r tssr r/w r/w dwr r/w r tar r/w - car r/w - lir r r rier r/w r/w riir r/c r/c ttr r/w - [15:0] aer rtc register access enable password (write only) 0xa965 = enable rtc access numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 329 - revision v1.06 others = disable rtc access numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 330 - revision v1.06 rtc frequency compensation register (fcr) register offset r/w description reset value fcr rtc_ba+0x08 r/w frequency compensation register 0x0000_0700 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved integer 7 6 5 4 3 2 1 0 reserved fraction bits descriptions [31:12] reserved reserved [11:8] integer integer part integer part of detected value fcr[11:8] integer part of detected value fcr[11:8] 32776 1111 32768 0111 32775 1110 32767 0110 32774 1101 32766 0101 32773 1100 32765 0100 32772 1011 32764 0011 32771 1010 32763 0010 32770 1001 32762 0001 32769 1000 32761 0000 [5:0] fraction fraction part formula = (fraction part of detected value) x 60 note: digit in fcr must be expressed as hexadecimal number. refer to 5.8.4.4 for the examples. note: this register can be read back after the rtc register access enable bit enf (aer[16]) is active. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 331 - revision v1.06 rtc time loading register (tlr) register offset r/w description reset value tlr rtc_ba+0x0c r/w time loading register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 10hr 1hr 15 14 13 12 11 10 9 8 reserved 10min 1min 7 6 5 4 3 2 1 0 reserved 10sec 1sec bits descriptions [31:22] reserved reserved [21:20] 10hr 10 hour time digit (0~2) [19:16] 1hr 1 hour time digit (0~9) [15] reserved reserved [14:12] 10min 10 min time digit (0~5) [11:8] 1min 1 min time digit (0~9) [7] reserved reserved [6:4] 10sec 10 sec time digit (0~5) [3:0] 1sec 1 sec time digit (0~9) note: 1. tlr is a bcd digit counter and rtc will not check loaded data. 2. the reasonable value range is listed in the parenthesis. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 332 - revision v1.06 rtc calendar loading register (clr) register offset r/w description reset value clr rtc_ba+0x10 r/w calendar loading register 0x0005_0101 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 10year 1year 15 14 13 12 11 10 9 8 reserved 10mon 1mon 7 6 5 4 3 2 1 0 reserved 10day 1day bits descriptions [31:24] reserved reserved [23:20] 10year 10-year calendar digit (0~9) [19:16] 1year 1-year calendar digit (0~9) [15:13] reserved reserved [12] 10mon 10-month calendar digit (0~1) [11:8] 1mon 1-month calendar digit (0~9) [7:6] reserved reserved [5:4] 10day 10-day calendar digit (0~3) [3:0] 1day 1-day calendar digit (0~9) note: 1. tlr is a bcd digit counter and rtc will not check loaded data. 2. the reasonable value range is listed in the parenthesis. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 333 - revision v1.06 rtc time scale selection register (tssr) register offset r/w description reset value tssr rtc_ba+0x14 r/w time scale selection register 0x0000_0001 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved 24h_12h bits descriptions [31:1] reserved reserved [0] 24h_12h 24-hour / 12-hour time scale selection it indicate that tlr and tar are in 24-hour time scale or 12-hour time scale 1 = select 24-hour time scale 0 = select 12-hour time scale with am and pm indication 24-hour time scale 12-hour time scale 24-hour time scale 12-hour time scale (pm time + 20) 00 12(am12) 12 32(pm12) 01 01 (am01) 13 21 (pm01) 02 02(am02) 14 22(pm02) 03 03(am03) 15 23(pm03) 04 04 (am04) 16 24 (pm04) 05 05(am05) 17 25(pm05) 06 06(am06) 18 26(pm06) 07 07(am07) 19 27(pm07) 08 08(am08) 20 28(pm08) 09 09(am09) 21 29(pm09) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 334 - revision v1.06 rtc day of the week register (dwr) register offset r/w description reset value dwr rtc_ba+0x18 r/w day of the week register 0x0000_0006 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved dwr bits descriptions [31:3] reserved reserved [2:0] dwr day of the week register value day of the week 0 sunday 1 monday 2 tuesday 3 wednesday 4 thursday 5 friday 6 saturday numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 335 - revision v1.06 rtc time alarm register (tar) register offset r/w description reset value tar rtc_ba+0x1c r/w time alarm register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 10hr 1hr 15 14 13 12 11 10 9 8 reserved 10min 1min 7 6 5 4 3 2 1 0 reserved 10sec 1sec bits descriptions [31:22] reserved reserved [21:20] 10hr 10 hour time digit of alarm setting (0~2) [19:16] 1hr 1 hour time digit of alarm setting (0~9) [15] reserved reserved [14:12] 10min 10 min time digit of alarm setting (0~5) [11:8] 1min 1 min time digit of alarm setting (0~9) [7] reserved reserved [6:4] 10sec 10 sec time digit of alarm setting (0~5) [3:0] 1sec 1 sec time digit of alarm setting (0~9) note: 1. tlr is a bcd digit counter and rtc will not check loaded data. 2. the reasonable value range is listed in the parenthesis. 3. this register can be read back after the rtc r egister access enable bit enf (aer[16]) is active. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 336 - revision v1.06 rtc calendar alarm register (car) register offset r/w description reset value car rtc_ba+0x20 r/w calendar alarm register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 10year 1year 15 14 13 12 11 10 9 8 reserved 10mon 1mon 7 6 5 4 3 2 1 0 reserved 10day 1day bits descriptions [31:24] reserved reserved [23:20] 10year 10-year calendar digit of alarm setting (0~9) [19:16] 1year 1-year calendar digit of alarm setting (0~9) [15:13] reserved reserved [12] 10mon 10-month calendar digit of alarm setting (0~1) [11:8] 1mon 1-month calendar digit of alarm setting (0~9) [7:6] reserved reserved [5:4] 10day 10-day calendar digit of alarm setting (0~3) [3:0] 1day 1-day calendar digit of alarm setting (0~9) note: 1. tlr is a bcd digit counter and rtc will not check loaded data. 2. the reasonable value range is listed in the parenthesis. 3. this register can be read back after the rtc r egister access enable bit enf (aer[16]) is active. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 337 - revision v1.06 rtc leap year indication register (lir) register offset r/w description reset value lir rtc_ba+0x24 r rtc leap year indication register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved lir bits descriptions [31:1] reserved reserved [0] lir leap year indication register (real only). 1 = it indicate that this year is leap year 0 = it indicate that this year is not a leap year numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 338 - revision v1.06 rtc interrupt enable register (rier) register offset r/w description reset value rier rtc_ba+0x28 r/w rtc interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved tier aier bits descriptions [31:2] reserved reserved [1] tier time tick interrupt enable 1 = rtc time tick interrupt is enabled 0 = rtc time tick interrupt is disabled [0] aier alarm interrupt enable 1 = rtc alarm interrupt is enabled 0 = rtc alarm interrupt is disabled numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 339 - revision v1.06 rtc interrupt indicat ion register (riir) register offset r/w description reset value riir rtc_ba+0x2c r/c rtc interrupt indication register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved tif aif bits descriptions [31:2] reserved reserved [1] tif rtc time tick interrupt flag when rtc time tick interrupt is enabled (rie r.tier=1), rtc controller will set tif to high periodically in the period selected by ttr[2:0]. this bit is software clear by writing 1 to it. 1= indicates rtc time tick interrupt is requested if rier.tier=1 0= indicates rct time tick interrupt condition never occurred. [0] aif rtc alarm interrupt flag when rtc alarm interrupt is enabled (rier.aier=1), rtc controller will set aif to high once the rtc real time counters tl r and clr reach the alarm setting time registers tar and car. this bit is software clear by writing 1 to it. 1= indicates rtc alarm interrupt is requested if rier.aier=1 0= indicates rct alarm interrupt condition never occurred. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 340 - revision v1.06 rtc time tick register (ttr) register offset r/w description reset value ttr rtc_ba+0x30 r/c rtc time tick register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved twke ttr[2:0] bits descriptions [31:4] reserved reserved [3] twke rtc timer wakeup cpu function enable bit if twke is set before cpu is in power-down mode, when a rtc time tick occurs, cpu will be wakened up by rtc controller. 1 = enable the wakeup function that cpu can be waken up from power-down mode by time tick. 0 = disable wakeup cpu function by time tick. note: 1. tick timer setting follows ttr[2:0] description. 2. the cpu can also be wakeup by alarm match occur. [2:0] ttr time tick register the rtc time tick period for peri odic time tick interrupt request. ttr[2:0] time tick (second) 0 1 1 1/2 2 1/4 3 1/8 4 1/16 5 1/32 6 1/64 7 1/128 note: this register can be read back after the rtc register access enable bit enf (aer[16]) is active. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 341 - revision v1.06 5.9 serial peripheral interface (spi) 5.9.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4-wire bi-direction interface. the numicro ? nuc100 medium density contains up to four sets of spi controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on dat a transmitted to a peripheral device. each set of spi controller can be set as a master that can drive up to 2 exte rnal peripheral slave devices; it also can be configured as a slave device controlled by an off-chip master device. numicro ? nuc100 low density contains two sets of spi controller only. this controller supports a variable serial clock for special application and it also supports 2 bit transfer mode to connect 2 off-chip slave devices at the same time. the spi controller also supports pdma function to access the data buffer. 5.9.2 features z up to four sets of spi controller for numicro ? nuc100 medium density z up to two sets of spi controller for numicro ? nuc100 low density z support master or slave mode operation z support 1-bit or 2-bit transfer mode z configurable bit length up to 32 bits of a transfer word and configurable word numbers up to 2 of a transaction, so the maximum bit length is 64 bits for each data transfer z provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer z support msb or lsb first transfer z 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode z support byte reorder in data register z support byte or word suspend mode z variable output serial clock frequency in master mode z support two programmable serial clock frequencies in master mode z support two channel pdma request, one for transmitter and another for receiver numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 342 - revision v1.06 5.9.3 block diagram apb interface control pdma control clock generator status/control register core logic tx buffer rx buffer pio misox1 misox0 mosix1 mosix0 spiclkx spissx0 spissx1 figure 5-49 spi block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 343 - revision v1.06 5.9.4 function description master/slave mode this spi controller can be set as master or slave mode by setting the slave bit (spi_cntrl[18]) to communicate with the off-ch ip spi slave or master device. the application block diagrams in master and slave mode are shown as below. this spi controller does not support multi-slave in spi bus if the controller is set as slave mode. spi controller master spiclkx misox mosix spissx0 spissx1 slave 0 sclk miso mosi ss slave 1 sclk miso mosi ss figure 5-50 spi master mode application block diagram figure 5-51 spi slave mode application block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 344 - revision v1.06 slave select in master mode, this spi controller can drive up to two off-chip slave devices through the slave select output pins spissx0 and spissx1. in slave mode, the off-chip master device drives the slave select signal from the spissx0 input port to this spi controller. in master/slave mode, the active level of slave select signal can be programmed to low active or high active in ss_lvl bit (spi_ssr[2]), and the ss_ltrig bi t (spi_ssr[4]) defines the slave select signal spissx0/1 is level trigger or edge trigger. the selection of trigger condition depends on what type of peripheral slave/master device is connected. in slave mode, if the ss_ltrig bit is configured as level trigger, the ltrig_flag bit (spi_ssr[5]) is used to indicate if both t he received number and received bits met the requirement which defines in tx_num and tx_bit_len among one transaction done (the transaction done means the slave select has deactivated.). level-trigger / edge-trigger in slave mode, the slave select signal can be configured as level-trigger or edge-trigger. in edge- trigger, the data transfer starts from an active edge and ends on an inactive edge. if master does not send an inactive edge to slave, the transfer procedure will not be completed and the interrupt flag of slave will not be set. in level-trigger, the following two conditions will terminate the transfer procedure and the interrupt flag of slave will be se t. the first condition, if master set the slave select pin to inactive level, it will force slave device to terminate the current transfer no matter how many bits have been transferred and the interrupt flag will be set. user can read the status of ltrig_flag bit to check if the data has been completely transferred. the second condition is that if the number of transferred bits matc hes the settings of tx_num and tx_bit_len, the interrupt flag of slave will be set. automatic slave select in master mode, if the bit autoss (spi_ssr[3]) is set, the slave select signals will be generated automatically and output to spissx0 and spissx1 pi ns according to ssr[0] (spi_ssr[0]) and ssr[1] (spi_ssr[1]) whether be enabled or not. it m eans that the slave select signals, which is enabled in ssr[1:0] register is asserted by the spi controller when transmit/receive is started by setting the go_busy bit (spi_cntrl[0]) and is de-asse rted after the data transfer is finished. if the autoss bit is cleared, the slave select output signals are asserted and de-asserted by manual setting and clearing the related bits in spi_ssr[1:0] register. the active level of the slave select output signals is specified in ss_lvl bit (spi_ssr[2]). serial clock in master mode, set the divider1 bits (spi_divider[15:0]) to program the output frequency of serial clock to the spiclk output port. it also supports a variable serial clock if the varclk_en bit (spi_ctl[23]) is enabled. in this case, the output frequency of serial clock can be programmed as one of the two different frequencies which depend on the value of divider1 (spi_divider[15:0]) and divider2 (spi_divider[ 31:16]). the decision of the variable serial clock for each cycle is depended on the spi_varclk register. in slave mode, the off-chip master device drives the serial clock through the spiclk input port to this spi controller. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 345 - revision v1.06 variable serial clock frequency in master mode, the output of serial clock can be programmed as variable frequency pattern if the variable clock enable bit varclk_en (spi_cntrl[23]) is enabled. the frequency pattern format is defined in varclk (spi_varclk[31:0]) re gister. if the bit content of varclk is ?0? the output frequency is according with the divider (spi_divider[15:0]) and if the bit content of varclk is ?1?, the output frequency is accord ing to the divider2 (spi_divider[31:16]). figure 5-52 is the timing relationship among the serial clock (spiclk), the varclk, the divider and the divider2 registers. a two-bit combination in the varclk defines one clock cycle. the bit field varclk[31:30] defines the first clock cycle of spiclk. the bit field varclk[29:28] defines the second clock cycle of spiclk and so on. the clock source selections are defined in varclk and it must be set 1 cycle before the next clock optio n. for example, if there are 5 clk1 cycle in spiclk, the varclk shall set 9 ?0? in the msb of varclk. the 10th shall be set as ?1? in order to switch the next clock source is clk2. note that when enable the varclk_en bit, the setting of tx_bit_len must be programmed as 0x10 (16 bits mode only). 00000000011111111111111110000111 spiclk varclk clk1 (divider) clk2 (divider2) figure 5-52 variable serial clock frequency clock polarity the clkp bit (spi_ctl[11]) defines the serial cloc k idle state in master mode only. if clkp = 1, the output spiclk is idle at high state, otherwise it is at low state if clkp = 0. for variable serial clock, it works in clkp = 0 only. transmit/receive bit length the bit length of a transaction word is defined in tx_bit_len bit field (spi_cntrl[7:3]). it can be configured up to 32 bits length in a transaction word for transmitting and receiving. figure 5-53 32-bit in one transaction numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 346 - revision v1.06 burst mode spi controller can switch to burst mode by setting tx_num bit field (spi_cntrl[9:8]) to 0x01. in burst mode, spi can transmit/receive two trans actions in one transfer. the spi burst mode waveform is showed below: figure 5-54 two transactions in one transfer (burst mode) lsb first the lsb bit (spi_cntrl[10]) defines the data tran smission either from lsb or msb firstly to start to transmit/receive data. transmit edge the tx_neg bit (spi_cntrl[2]) defines the data transmitted out either at negative edge or at positive edge of serial clock spiclk. receive edge the rx_neg bit (spi_cntrl[1]) defines the dat a received in either at negative edge or at positive edge of serial clock spiclk. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 347 - revision v1.06 word suspend these four bits field of sp_cycle (spi_cntrl [15:12]) provide a configurable suspend interval 2 ~ 17 serial clock periods between two successive transaction words in master mode. the suspend interval is from the last falling clock edge of the preceding transaction word to the first rising clock edge of the following transaction word if clkp = 0. if clkp = 1, the interval is from the rising clock edge of the preceding transaction word to the falling clock edge of the following transaction word. the default value of sp_cycle is 0x0 (2 serial clock cycles), but set these bits field has no any effects on data transaction process if tx_num = 0x00. byte reorder when the transfer is set as msb first (lsb = 0) and the reorder is enabled, the data stored in the tx buffer and rx buffer will be rearranged in the order as [byte0, byte1, byte2, byte3] in tx_bit_len = 32 bits mode, and the sequence of transmitted/received data will be byte0, byte1, byte2, and then byte3. if t he tx_bit_len is set as 24-bits mode, the data in tx buffer and rx buffer will be rearranged as [unknown byte, byte0, byte1, byte2] and the byte0, byte1, and byte2 will be transmitted/received data step by step in msb first. the rule of 16-bits mode is the same as above. byte3 byte0 byte1 byte2 spi_tx0/spi_rx0 tx/rx buffer lsb = 0 (msb first) & reorder = 2'b10/2'b01 tx_bit_len = 24 bits tx_bit_len = 16 bits tx_bit_len = 32 bits msb first msb first nn = unknown byte nn byte1 byte0 nn byte1 byte0 nn byte2 msb first byte3 byte0 byte1 byte2 msb first figure 5-55 byte reorder numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 348 - revision v1.06 byte suspend in master mode, if spi_cntrl[19] is set to 1, the hardware will insert a suspend interval 2 ~ 17 serial clock periods between two successive by tes in a transaction word. the byte suspend setting is the same as the word that using the common bit field of sp_cycle register. note that when enable the byte suspend function, the setting of tx_bit_len must be programmed as 0x00 only (32 bits per transaction word). figure 5-56 timing waveform for byte suspend reorder description 00 disable both byte reorder function and byte suspend interval. 01 enable byte reorder function and insert a byte suspend internal (2~17 spiclk) among each byte. the setting of tx_bit_len must be configured as 0x00 ( 32 bits/ word) 10 enable byte reorder function but disable byte suspend function 11 disable byte reorder function, but insert a suspend interval (2~17 spiclk) among each byte. the setting of tx_bit_len must be configured as 0x00 ( 32 bits/ word) table 5-6 byte order and byte suspend conditions interrupt each spi controller can generates an individual in terrupt when data transfer is finished and the respective interrupt event flag if (spi_cntrl[1 6]) will be set. the interrupt event flag will generates an interrupt to cpu if the interrupt en able bit ie (spi_cntrl[17]) is set. the interrupt event flag if can be cleared only by writing 1 to it. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 349 - revision v1.06 two bit transfer mode this spi controller also supports two-bit transfer mode when enabling the twob bit (spi_cntrl[22]). when the twob bit is enabled, it can transmit and receives two-bit serial data simultaneously. the 1 st bit through the mosix0 and misox0 pins to transmit the data from the spi_tx0 register and receive the data into the spi_rx0 register. the 2 nd bit through the mosix1 and misox1 pins to transmit the data from the spi_tx1 register and receive the data into the spi_rx1 register. note that when enable the twob bit, the setting of tx_num must be programmed as 0x00 only. figure 5-57 two bits transfer mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 350 - revision v1.06 5.9.5 timing diagram in master/slave mode, the active level of dev ice/slave select (spissx) signal can be programmed to low active or high active in ss_lvl bit (spi_ssr[2]), but the spissx0/1 is level trigger or edge trigger which is defined in ss_ltrig bit (spi_ssr[4 ]). the serial clock (spiclk) idle state can be configured as high state or low state by setti ng the clkp bit (spi_cntrl[11]). it also provides the bit length of a transaction word in tx_bit _len (spi_cntrl[7:3]), t he transfer number in tx_num (spi_cntrl[8]), and transmit/receive data from msb or lsb first in lsb bit (spi_cntrl[10]). users also can select which edge of serial clock to transmit/receive data in tx_neg/rx_neg (spi_cntrl[2:1]) registers. four spi timing diagrams for master/slave operations and the related settings are shown as below. spiclk miso mosi tx0[6] tx0[4] tx0[3] tx0[2] lsb tx0[0] rx0[6] rx0[4] rx0[2] lsb rx0[0] msb rx0[7] rx0[3] msb tx0[7] spiss clkp=0 clkp=1 tx0[5] rx0[5] tx0[1] rx0[1] ss_lvl=0 ss_lvl=1 master mode: cntrl[slvae]=0, cntrl[lsb]=0, cntrl[tx_num]=0x0, cntrl[tx_bit_len]=0x08 1. cntrl[clkp]=0, cntrl[tx_neg]=1, cntrl[rx_neg]=0 or 2. cntrl[clkp]=1, cntrl[tx_neg]=0, cntrl[rx_neg]=1 figure 5-58 spi timing in master mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 351 - revision v1.06 spiclk miso mosi tx0[1] tx0[3] tx0[4] tx0[5] msb tx0[7] rx0[1] rx0[3] rx0[5] msb rx0[7] lsb rx0[0] rx0[4] lsb tx0[0] spiss clkp=0 clkp=1 tx0[2] rx0[2] tx0[6] rx0[6] ss_lvl=0 ss_lvl=1 master mode: cntrl[slvae]=0, cntrl[lsb]=1, cntrl[tx_num]=0x0, cntrl[tx_bit_len]=0x08 1. cntrl[clkp]=0, cntrl[tx_neg]=0, cntrl[rx_neg]=1 or 2. cntrl[clkp]=1, cntrl[tx_neg]=1, cntrl[rx_neg]=0 figure 5-59 spi timing in master mode (alternate phase of spiclk) figure 5-60 spi timing in slave mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 352 - revision v1.06 spiclk mosi miso tx0[1] tx0[7] tx1[0] tx1[1] msb tx1[7] rx0[1] rx0[7] rx1[1] msb rx1[7] lsb rx0[0] rx1[0] lsb tx0[0] spiss clkp=0 clkp=1 ss_lvl=0 ss_lvl=1 slave mode: cntrl[slvae]=1, cntrl[lsb]=1, cntrl[tx_num]=0x01, cn trl[tx_bit_len]=0x08 1. cntrl[clkp]=0, cntrl[tx_n eg]=0, cntrl[rx_neg]=1 or 2. cntrl[clkp]=1, cntrl[tx _neg]=1, cntrl[rx_neg]=0 figure 5-61 spi timing in slave mode (alternate phase of spiclk) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 353 - revision v1.06 5.9.6 programming examples example 1, spi controller is set as a master to access an off-chip slave device with following specifications: z data bit is latched on positive edge of serial clock z data bit is driven on negative edge of serial clock z data is transferred from msb first z spiclk is idle at low state z only one byte of data to be transmitted/received in a transaction z slave select signal is active low basically, the specification of the connected off- chip slave device should be referred in details before the following steps: 1. set the divider (spi_divider[15:0]) register to determine the output frequency of serial clock. 2. write the spi_ssr register a proper value fo r the related settings of master mode, in this case, for example, to disable the automati c slave select bit autoss (spi_ssr[3] = 0), select low level trigger output of slave select signal in the slave select active level bit ss_lvl (spi_ssr[2] = 0), and select which slave select signal will be output at the io pin by setting the respective slave select regist er bits ssr[0] or ssr[1 ] (spi_ssr[1:0]) to active the off-chip slave devices. 3. write the related settings into the spi_cntrl register to control this spi master actions, set this spi controller as master device in slave bit (spi_cntrl[18] = 0), force the serial clock idle state at low in clkp bit (spi_cntrl[11] = 0), select data transmitted at negative edge of serial clock in tx_neg bit (spi_cnt rl[2] = 1), select data latched at positive edge of serial clock in rx_neg bit (spi_cntrl[1] = 0), set the bit length of word transfer as 8 bits in tx_bit_len bit field (spi_cntrl[7:3] = 0x08), set only one time of word transaction in tx_num (spi_cntrl[9:8] = 0x0), set msb transfer first in lsb bit (spi_cntrl[10] = 0), and don?t care the sp_ cycle bit field (spi_cntrl[15:12]) due to not burst mode in this case. 4. if this spi master will transmits (writes) one byte data to the off-chip slave device, write the byte data that will be transmitted into the tx0[7:0] (spi_tx0[7:0]) register. 5. if this spi master just only receives (reads) one byte data from the off-chip slave device, you don?t need to care what data will be transmitted and just write 0xff into the spi_tx0[7:0] register. 6. enable the go_busy bit (spi_cntrl[0] = 1) to start the data transfer at the spi interface. 7. waiting for spi interrupt occurred (if the interrupt enable ie bit is set) or just polling the go_busy bit till it be cleared to 0 by hardware automatically. 8. read out the received one byte data fr om rx0[7:0] (spi_rx0[7:0]) register. 9. go to 4) to continue another data transfer or set ssr[0] or ssr[1] to 0 to inactivate the off- chip slave devices. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 354 - revision v1.06 example 2, spi controller is set as a slave device that controlled by an off-chip master device, and supposes the off-chip master device to access the on-chip spi slave controller through the spi interface with the following specifications: z data bit is latched on positive edge of serial clock z data bit is driven on negative edge of serial clock z data is transferred from lsb first z spiclk is idle at high state z only one byte of data to be transmitted/received in a transaction z slave select signal is high level trigger basically, the specification of the connected off- chip master device should be referred in details before the following steps: 1. select high level and level trigger for the input of slave select signal in the slave select active level bit ss_lvl (spi_ssr[2] = 1) and the slave select level trigger bit ss_ltrig (spi_ssr[4] = 1). 2. write the related settings into the spi_cntrl register to control this spi slave actions, set this spi controller as slave device in slave bi t (spi_cntrl[18] = 1), select the serial clock idle state at high in clkp bit (spi_cntrl[11] = 1), select data transmitted at negative edge of serial clock in tx_neg bit (spi_cntrl[2] = 1), select data latched at positive edge of serial clock in rx_neg bit (spi_cntrl[1] = 0), set the bit length of word transfer as 8 bits in tx_bit_len bit field (spi_cntrl[7:3] = 0x08), set only one time of word transaction in tx_num (spi_cntrl[9:8 ] = 0x0), set lsb transfer first in lsb bit (spi_cntrl[10] = 1), and don?t care the sp_ cycle bit field (spi_cntrl[15:12]) due to not burst mode in this case. 3. if this spi slave will transmits (be read) one by te data to the off-chip master device, write the byte data that will be transmitted into the tx0[7:0] (spi_tx0[7:0]) register. 4. if this spi slave just only receives (be wri tten) one byte data from the off-chip master device, you don?t care what data will be transmitted and just write 0xff into the spi_tx0[7:0] register. 5. enable the go_busy bit (spi_cntrl[0] = 1) to wait for the slave select trigger input and serial clock input from the off-chip master device to start the data transfer at the spi interface. 6. waiting for spi interrupt occurred (if the interrupt enable ie bit is set) or just polling the go_busy bit till it be cleared to 0 by hardware automatically. 7. read out the received one byte data from rx[7:0] (spi_r x0[7:0]) register. 8. go to 3) to continue another data transfer or disable the go_busy bit to stop data transfer. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 355 - revision v1.06 5.9.7 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value spi0_ba = 0x4003_0000 spi1_ba = 0x4003_4000 spi2_ba = 0x4013_0000 spi3_ba = 0x4013_4000 spi_cntrl spix_ba+0x00 r/w control and status register 0x0500_0004 spi_divider spix_ba+0x04 r/w clock divider register 0x0000_0000 spi_ssr spix_ba+0x08 r/w slave select register 0x0000_0000 spi_rx0 spix_ba+0x10 r data receive register 0 0x0000_0000 spi_rx1 spix_ba+0x14 r data receive register 1 0x0000_0000 spi_tx0 spix_ba+0x20 w data transmit register 0 0x0000_0000 spi_tx1 spix_ba+0x24 w data transmit register 1 0x0000_0000 spi_varclk spix_ba+0x34 r/w variable clock pattern register 0x007f_ff87 spi_dma spix_ba+0x38 r/w spi dma control register 0x0000_0000 note: when software programs cntrl, the go_busy bit should be written last. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 356 - revision v1.06 5.9.8 register description spi control and status register (spi_cntrl) register offset r/w description reset value spi_cntrl spix_ba+0x00 r/w control and status register 0x0500_0004 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 varclk_en twob reserved reorder slave ie if 15 14 13 12 11 10 9 8 sp_cycle clkp lsb tx_num 7 6 5 4 3 2 1 0 tx_bit_len tx_neg rx_neg go_busy bits descriptions [31:24] reserved reserved [23] varclk_en variable clock enable (master only) 1 = the serial clock output frequency is va riable. the output frequency is decided by the value of varclk, divider, and divider2. 0 = the serial clock output frequency is fixed and decided only by the value of divider. note that when enable this varclk_en bit, the setting of tx_bit_len must be programmed as 0x10 (16 bits mode) [22] twob two bits transfer mode active 1 = enable two-bit transfer mode. 0 = disable two-bit transfer mode. note that when enable twob, the serial transmitted 2-bit data output are from spi_tx1/0, and the received 2-bit data input are put in spi_rx1/0. note that when enable twob, the setting of tx_num must be programmed as 0x00 [21] reserved reserved [20:19] reorder reorder mode select 00 = disable both byte reorde r and byte suspend functions. 01 = enable byte reorder function and insert a byte suspend interval (2~17 spiclk cycles) among each byte. the setting of tx_bit_len must be configured as 0x00. (32 bits/word) 10 = enable byte reorder function, but disable byte suspend function. 11 = disable byte reorder function, but inse rt a suspend interval (2~17 spiclk cycles) among each byte. the setting of tx_bit_len must be configured as 0x00. (32 bits/word) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 357 - revision v1.06 byte reorder function is only available if tx_bit_len is defined as 16, 24, and 32 bits. [18] slave slave mode indication 1 = slave mode 0 = master mode [17] ie interrupt enable 1 = enable spi/microwire interrupt 0 = disable spi/microwire interrupt [16] if interrupt flag 1 = it indicates that the transfer is done. the interrupt flag is set if it was enable. 0 = it indicates that the transfer dose not finish yet. note: this bit is cleared by writing 1 to itself. [15:12] sp_cycle suspend interval (master only) these four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. the suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if clkp = 0. if clkp = 1, the inte rval is from the rising clock edge to the falling clock edge. the default value is 0x0. when tx_num = 00b, setting this field has no effect on transfer. the desired suspend interval is obtained according to the following equation: (sp_cycle[3:0] + 2) * period of spiclk sp_cycle = 0x0 ? 2 spiclk clock cycle sp_cycle = 0x1 ? 3 spiclk clock cycle ?? sp_cycle = 0xe ? 16 spiclk clock cycle sp_cycle = 0xf ? 17 spiclk clock cycle [11] clkp clock polarity 1 = spiclk idle high 0 = spiclk idle low [10] lsb lsb first 1 = the lsb is sent first on the line (bit 0 of spi_tx0/1), and the first bit received from the line will be put in the lsb position in the rx register (bit 0 of spi_rx0/1). 0 = the msb is transmitted/received first (which bit in spi_tx0/1 and spi_rx0/1 register that is depends on the tx_bit_len field). [9:8] tx_num numbers of transmit/receive word this field specifies how many transmit/rec eive word numbers should be executed in one transfer. 00 = only one transmit/receive word will be executed in one transfer. 01 = two successive transmit/receive words will be executed in one transfer. (burst mode) 10 = reserved. 11 = reserved. [7:3] tx_bit_len transmit bit length this field specifies how many bits are transm itted in one transaction. up to 32 bits can be transmitted. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 358 - revision v1.06 tx_bit_len = 0x01 ? 1 bit tx_bit_len = 0x02 ? 2 bits ?? tx_bit_len = 0x1f ? 31 bits tx_bit_len = 0x00 ? 32 bits [2] tx_neg transmit at negative edge 1 = the transmitted data output signal is changed at the falling edge of spiclk 0 = the transmitted data output signal is changed at the rising edge of spiclk [1] rx_neg receive at negative edge 1 = the received data input signal is latched at the falling edge of spiclk 0 = the received data input signal is latched at the rising edge of spiclk [0] go_busy go and busy status 1 = in master mode, writing 1 to this bit to start the spi data transfer; in slave mode, writing 1 to this bit indicates that the sl ave is ready to communicate with a master. 0 = writing 0 to this bit to stop data transfer if spi is transferring. during the data transfer, this bit keeps the val ue of 1. as the transfer is finished, this bit will be cleared automatically. note: all registers should be set before writ ing 1 to this go_busy bit. when a transfer is in progress, writing to any register of the spi/microwire master/slave core has no effect. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 359 - revision v1.06 spi divider register (spi_divider) register offset r/w description reset value spi_divider spix_ba+0x04 r/w clock divider r egister (master only) 0x0000_0000 31 30 29 28 27 26 25 24 divider2[15:8] 23 22 21 20 19 18 17 16 divider2[7:0] 15 14 13 12 11 10 9 8 divider[15:8] 7 6 5 4 3 2 1 0 divider[7:0] bits descriptions [31:16] divider2 clock divider 2 register (master only) the value in this field is the 2 nd frequency divider of the system clock, pclk, to generate the serial clock on the output spiclk. the desired frequency is obtained according to the following equation: 2*)12( + = divider f f pclk sclk [15:0] divider clock divider register (master only) the value in this field is the frequency divi der of the system clock, pclk, to generate the serial clock on the output spiclk. the desired frequency is obtained according to the following equation: 2*)1 ( + = divider f f pclk sclk in slave mode, the period of spi clock driven by a master shall equal or over 5 times the period of pclk. in other words, the maximum frequency of spi clock is the fifth of the frequency of slave?s pclk. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 360 - revision v1.06 spi slave select register (spi_ssr) register offset r/w description reset value spi_ssr spi0_ba+0x08 r/w slave select register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ltrig_flag ss_ltrig autoss ss_lvl ssr bits descriptions [31:6] reserved reserved [5] ltrig_flag level trigger flag when the ss_ltrig bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. 1 = the transaction number and the transferred bit length met the specified requirements which defined in tx_num and tx_bit_len. 0 = the transaction number or the transferred bit length of one transaction doesn't meet the specified requirements. note: this bit is read only [4] ss_ltrig slave select level trigger (slave only) 1 = the slave select signal will be level- trigger. it depends on ss_lvl to decide the signal is active low or active high. 0 = the input slave select signal is edge-trigger. this is the default value. [3] autoss automatic slave select (master only) 1 = if this bit is set, spissx0/1 signals ar e generated automatically. it means that device/slave select signal, which is set in ssr[1:0] register is asserted by the spi controller when transmit/receive is st arted by setting go_busy, and is de- asserted after each transmi t/receive is finished. 0 = if this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in ssr[1:0] register. [2] ss_lvl slave select active level it defines the active level of slave select signal (spissx0/1). 1 = the slave select signal spissx0/1 is active at high-level/rising-edge. 0 = the slave select signal spissx0/1 is active at low-level/falling-edge. [1:0] ssr slave select register (master only) if autoss bit is cleared, writing 1 to any bi t location of this field sets the proper spissx0/1 line to an active state and writing 0 sets the line back to inactive state. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 361 - revision v1.06 if autoss bit is set, writing 1 to any bit location of this field will select appropriate spissx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive st ate for the rest of the time. (the active level of spissx0/1 is specified in ss_lvl). note: 1. this interface can only drive one device/sl ave at a given time. therefore, the slave select pin of the selected device must be set to its active level before starting any read or write transfer. 2. spissx0 is also defined as device/ slave select input in slave mode. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 362 - revision v1.06 spi data receive register (spi_rx) register offset r/w description reset value spi_rx0 spix_ba+0x10 r data receive register 0 0x0000_0000 spi_rx1 spix_ba+0x14 r data receive register 1 0x0000_0000 31 30 29 28 27 26 25 24 rx[31:24] 23 22 21 20 19 18 17 16 rx[23:16] 15 14 13 12 11 10 9 8 rx[15:8] 7 6 5 4 3 2 1 0 rx[7:0] bits descriptions [31:0] rx data receive register the data receive registers hold the value of received data of the last executed transfer. valid bits depend on the transmit bit length field in the spi_cntrl register. for example, if tx_bit_len is set to 0x08 and tx_num is set to 0x0, bit rx0[7:0] holds the received data. note: the data receive registers are read only registers. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 363 - revision v1.06 spi data transmit register (spi_tx) register offset r/w description reset value spi_tx0 spix_ba+0x20 w data transmit register 0 0x0000_0000 spi_tx1 spix_ba+0x24 w data transmit register 1 0x0000_0000 31 30 29 28 27 26 25 24 tx[31:24] 23 22 21 20 19 18 17 16 tx[23:16] 15 14 13 12 11 10 9 8 tx[15:8] 7 6 5 4 3 2 1 0 tx[7:0] bits descriptions [31:0] tx data transmit register the data transmit registers hold the data to be transmitted in the next transfer. valid bits depend on the transmit bit length field in the cntrl register. for example, if tx_bit_len is set to 0x08 and the tx_num is set to 0x0, the bit tx0[7:0] will be transmitted in next transfe r. if tx_bit_len is set to 0x00 and tx_num is set to 0x1, the core will per form two 32-bit transmit/receive successive using the same setting (the order is tx0[31:0], tx1[31:0]). numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 364 - revision v1.06 spi variable clock pattern register (spi_varclk) register offset r/w description reset value spi_varclk spix_ba+0x34 r/w variable clock pattern register 0x007f_ff87 31 30 29 28 27 26 25 24 varclk[31:24] 23 22 21 20 19 18 17 16 varclk[23:16] 15 14 13 12 11 10 9 8 varclk[15:8] 7 6 5 4 3 2 1 0 varclk[7:0] bits descriptions [31:0] varclk variable clock pattern the value in this field is the frequency patterns of the spi clock. if the bit pattern of varclk is ?0?, the output frequency of spiclk is according the value of divider. if the bit patterns of varclk are ?1?, the output frequency of spiclk is according the value of divider2. refer to register spi_divider. refer to va riable clock paragraph for more detail description. note: it is used for clkp = 0 only. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 365 - revision v1.06 dma control register (dmactl) register offset r/w description reset value spi_dma spix_ba+0x38 r/w spi dma mode control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved rx_dma_go tx_dma_go bits descriptions [31:2] reserved reserved [1] rx_dma_go receive dma start set this bit to 1 will start the receive pdma process. spi controller will issue request to pdma controller automatically. hardware will auto clear this bit to 0 after pdma function done. [0] tx_dma_go transmit dma start set this bit to 1 will start the transmit pdma process. spi controller will issue request to pdma controller automatically. if using pdma mode to transfer data, remember not to set go_busy bit of spi_cntrl register. the dma controller inside spi controller will set it automatically whenever necessary. hardware will auto clear this bit to 0 after pdma function done. note: in dma mode, the burst mode is not support. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 366 - revision v1.06 5.10 timer controller (tmr) 5.10.1 overview the timer controller includes four 32-bit timers , timer0~timer3, which allows user to easily implement a timer control for applications. the timer can perform functions like frequency measurement, event counting, inte rval measurement, clock generati on, delay timing, and so on. the timer can generates an interrupt signal upon timeout, or provide the current value during operation. note: event counting function only support in numicro ? nuc100 low density. 5.10.2 features z 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter z independent clock source for each timer z provides one-shot, periodic, toggle an d auto-reload counting operation modes z time out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit tcmp) z maximum counting cycle time = (1 / 25 mhz) * (2^8) * (2^24), if timer clock is 25 mhz z 24-bit timer value is readable through tdr (timer data register) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 367 - revision v1.06 5.10.3 block diagram each channel is equipped with an 8-bit pre-scal e counter, a 24-bit up-timer, a 24-bit compare register and an interrupt request signal. refer to figure 5-62 for the timer controller block diagram. the re are five options of clock sources for each channel. figure 5-63 illustrates the clo ck source control function. figure 5-62 timer controller block diagram figure 5-63 clock source of timer controller numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 368 - revision v1.06 5.10.4 function description timer controller provides one-shot, period and t oggle modes operation. each operating function mode is shown as following: 5.10.4.1 one ?shot mode if timer is operated at one-shot mode and cen (timer enable bit) is set to 1, the timer counter starts up counting. once the timer counter value reaches timer compare register (tcmpr) value, if ie (interrupt enable bit) is set to 1?b1, then the timer interrupt flag is set and the interrupt signal is generated and sent to nvic to inform cpu. it indicates that the timer counting overflow happens. if ie (interrupt enable bit) is set to 0, no interrupt signal is generated. in this operating mode, once the timer counter value reaches time r compare register (tcmpr) value, the timer counter value goes back to counting initial value and cen (timer enable bit) is cleared to 0 by timer controller. timer counting operation stops, once the timer counter value reaches timer compare register (tcmpr) value. that is to say, timer operates timer counting and compares with tcmpr value function only one time after programming the timer compare register (tcmpr) value and cen (timer enable bit) is set to 1. so , this operating mode is called one-shot mode. 5.10.4.2 periodic mode if timer is operated at period mode and cen (timer enable bit) is set to 1, the timer counter starts up counting. once the timer counter value reaches timer compare register (tcmpr) value, if ie (interrupt enable bit) is set to 1?b1, then the ti mer interrupt flag is set and the interrupt signal is generated and sent to nvic to inform cpu. it i ndicates that the timer counting overflow happens. if ie (interrupt enable bit) is set to 0, no interrupt signal is generated. in this operating mode, once the timer counter value reaches timer compare r egister (tcmpr) value, the timer counter value goes back to counting initial value and cen is kept at 1 (counting enable continuously). the timer counter operates up counting again. if the interrupt flag is cleared by software, once the timer counter value reaches timer compare register (tcmpr) value and ie (interrupt enable bit) is set to 1?b1, then the timer interrupt flag is set and the interrupt signal is generated and sent to nvic to inform cpu again. that is to say, timer operates timer counting and compares with tcmpr value function periodically. the timer counting operation doesn?t stop until the cen is set to 0. the interrupt signal is also generated periodically. so, this operating mode is called periodic mode. 5.10.4.3 toggle mode if timer is operated at toggle mode and cen (timer enabl e bit) is set to 1, the timer counter starts up counting. once the timer counter value reaches timer compare register (tcmpr) value, if ie (interrupt enable bit) is set to 1?b1, then the ti mer interrupt flag is set and the interrupt signal is generated and sent to nvic to inform cpu. it i ndicates that the timer counting overflow happens. the associated toggle output (tout) signal is set to 1. in this operating mode, once the timer counter value reaches timer compare register (t cmpr) value, the timer counter value goes back to counting initial value and cen is kept at 1 (counting enable continuously). the timer counter operates up counting again. if the interrupt flag is cleared by software, once the timer counter value reaches timer compare register (tcmpr) value and ie (interrupt enable bit) is set to 1, then the timer interrupt flag is set and the interrupt sig nal is generated and sent to nvic to inform cpu again. the associated toggle output (tout) signal is set to 0. the timer counting operation doesn?t stop until the cen is set to 0. thus, the toggle out put (tout) signal is changing back and forth with 50% duty cycle. so, this operating mode is called toggle mode. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 369 - revision v1.06 5.10.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value tmr_ba01 = 0x4001_0000 tmr_ba23 = 0x4011_0000 tcsr0 tmr_ba01+0x00 r/w timer0 control and status register 0x0000_0005 tcmpr0 tmr_ba01+0x04 r/w timer0 compare register 0x0000_0000 tisr0 tmr_ba01+0x08 r/w timer0 interrupt status register 0x0000_0000 tdr0 tmr_ba01+0x0c r timer0 data register 0x0000_0000 tcsr1 tmr_ba01+0x20 r/w timer1 control and status register 0x0000_0005 tcmpr1 tmr_ba01+0x24 r/w timer1 compare register 0x0000_0000 tisr1 tmr_ba01+0x28 r/w timer1 interrupt status register 0x0000_0000 tdr1 tmr_ba01+0x2c r timer1 data register 0x0000_0000 tcsr2 tmr_ba23+0x00 r/w timer2 control and status register 0x0000_0005 tcmpr2 tmr_ba23+0x04 r/w timer2 compare register 0x0000_0000 tisr2 tmr_ba23+0x08 r/w timer2 interrupt status register 0x0000_0000 tdr2 tmr_ba23+0x0c r timer2 data register 0x0000_0000 tcsr3 tmr_ba23+0x20 r/w timer3 control and status register 0x0000_0005 tcmpr3 tmr_ba23+0x24 r/w timer3 compare register 0x0000_0000 tisr3 tmr_ba23+0x28 r/w timer3 interrupt status register 0x0000_0000 tdr3 tmr_ba23+0x2c r timer3 data register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 370 - revision v1.06 5.10.6 register description timer control register (tcsr) register offset r/w description reset value tcsr0 tmr_ba01+0x00 r/w timer0 control and status register 0x0000_0005 tcsr1 tmr_ba01+0x20 r/w timer1 control and status register 0x0000_0005 tcsr2 tmr_ba23+0x00 r/w timer2 control and status register 0x0000_0005 tcsr3 tmr_ba23+0x20 r/w timer3 control and status register 0x0000_0005 31 30 29 28 27 26 25 24 reserved cen ie mode[1:0] crst cact ctb 23 22 21 20 19 18 17 16 reserved tdr_en 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 prescale[7:0] bits descriptions [31] reserved reserved [30] cen timer enable bit 1 = starts counting 0 = stops/suspends counting note1: in stop status, and then set cen to 1 will enables the 24-bit up-timer keeps up counting from the last stop counting value. note2: this bit is auto-cleared by hardware in one-shot mode (mode [28:27] =00) when the associated timer interrupt is generated (ie [29] =1). [29] ie interrupt enable bit 1 = enable timer interrupt 0 = disable timer interrupt if timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to tcmpr. [28:27] mode timer operating mode mode timer operating mode 00 the timer is operating in the one-shot mode. the associated interrupt signal is generated once (if ie is enabled) and cen is automatically numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 371 - revision v1.06 cleared by hardware. 01 the timer is operating in the periodic mode. the associated interrupt signal is generated periodica lly (if ie is enabled). 10 the timer is operating in the t oggle mode. the interrupt signal is generated periodically (if ie is enabled). and the associated signal (tout) is changing back and forth with 50 % duty cycle. (this mode only supported in low density) 11 the timer is operating in auto-reload counting mode. the associated interrupt signal is generated when tdr = tcmpr (if ie is enabled); however, the 24-bit up-timer counts continuously without reset. (this mode only supported in low density) [26] crst timer reset bit set this bit will reset the 24-bit up-timer, 8- bit pre-scale counter and also force cen to 0. 0 = no effect 1 = reset timer?s 8-bit pre-scale counter , internal 24-bit up-timer and cen bit [25] cact timer active status bit (read only) this bit indicates the up-timer status. 0 = timer is not active 1 = timer is active [24] ctb counter mode enable bit (low density only) this bit is the counter mode enable bit. w hen timer is used as an event counter, this bit should be set to 1 and timer will work as an event counter triggered by raising edge of external pin. 1 = enable counter mode 0 = disable counter mode [23:17] reserved reserved [16] tdr_en data load enable when tdr_en is set, tdr (timer data register) will be updated continuously with the 24-bit up-timer value as the timer is counting. 1 = timer data register update enable 0 = timer data register update disable [15:8] reserved reserved [7:0] prescale pre-scale counter clock input is divided by prescale+1 before it is fed to the counter. if prescale = 0, then there is no scaling. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 372 - revision v1.06 timer compare register (tcmpr) register offset r/w description reset value tcmpr0 tmr_ba01+0x04 r/w timer0 compare register 0x0000_0000 tcmpr1 tmr_ba01+0x24 r/w timer1 compare register 0x0000_0000 tcmpr2 tmr_ba23+0x04 r/w timer2 compare register 0x0000_0000 tcmpr3 tmr_ba23+0x24 r/w timer3 compare register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 tcmp [23:16] 15 14 13 12 11 10 9 8 tcmp [15:8] 7 6 5 4 3 2 1 0 tcmp [7:0] bits descriptions [31:24] reserved reserved [23:0] tcmp timer compared value tcmp is a 24-bit compared register. when the internal 24-bit up-timer counts and its value is equal to tcmp value, a timer interr upt is requested if the timer interrupt is enabled with tcsr.ie[29]=1. the tcmp value defines the timer counting cycle time. time out period = (period of timer clock i nput) * (8-bit prescale + 1) * (24-bit tcmp) note1: never write 0x0 or 0x1 in tcmp, or the core will run into unknown state. note2: no matter cen is 0 or 1, whenever software write a new value into this register, timer will restart counting using this new value and abort previous count. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 373 - revision v1.06 timer interrupt status register (tisr) register offset r/w description reset value tisr0 tmr_ba01+0x08 r/w timer0 interrupt status register 0x0000_0000 tisr1 tmr_ba01+0x28 r/w timer1 interrupt status register 0x0000_0000 tisr2 tmr_ba23+0x08 r/w timer2 interrupt status register 0x0000_0000 tisr3 tmr_ba23+0x28 r/w timer3 interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved tif bits descriptions [31:1] reserved reserved [0] tif timer interrupt flag this bit indicates the interrupt status of timer. tif bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (tcmp). it is cleared by writing 1 to this bit. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 374 - revision v1.06 timer data register (tdr) register offset r/w description reset value tdr0 tmr_ba01+0x0c r/w timer0 data register 0x0000_0000 tdr1 tmr_ba01+0x2c r/w timer1 data register 0x0000_0000 tdr2 tmr_ba23+0x0c r/w timer2 data register 0x0000_0000 tdr3 tmr_ba23+0x2c r/w timer3 data register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 tdr[23:16] 15 14 13 12 11 10 9 8 tdr[15:8] 7 6 5 4 3 2 1 0 tdr[7:0] bits descriptions [31:24] reserved reserved [23:0] tdr timer data register when tcsr.tdr_en is set to 1, the inte rnal 24-bit up-timer value will be loaded into tdr. user can read this register for the up-timer value. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 375 - revision v1.06 5.11 watchdog timer (wdt) 5.11.1 overview the purpose of watchdog timer is to perform a sy stem reset when system runs into an unknown state. this prevents system fr om hanging for an infinite period of time. besides, this watchdog timer supports another function to wakeup cpu from power-down mode. the watchdog timer includes a 18-bit free running counter with programmable time-out intervals. table 5-7 show the watchdo g timeout interval selection and figure 5-64 shows the timing of watchdog interrupt signal and reset signal. setting wte (wdtcr [7]) enables the watchdog ti mer and the wdt counter starts counting up. when the counter reaches the selected time-out interval, watchdog timer interrupt flag wtif will be set immediately to request a wdt interrupt if the watchdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time-out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to reset the 18-bit wdt counter to avoid cpu from watchdog timer reset before the delay time expires. wtr bit is cleared automatically by hardware after wdt counter is reset. there are eight time-out intervals with specific delay time which are selected by watchdog timer interval select bits wtis (wdtcr [10:8]). if the wdt counter has not been cleared after the specific del ay time expires, the watchdog timer will set watchdog timer reset flag (wtrf) high and reset cpu. this reset will last 63 wdt clocks (t rst ) then cpu restarts executing program from reset vector (0x0000_0000). wtrf will not be cleared by watchdog reset. user may poll wtfr by software to recognize the reset source. wdt also provides wakeup function. when chip is powered down and the watchdog timer wakeup function enable bit (wdtr[4]) is set, if the wdt counter has not been cleared after the specific delay time expires, the chip will be waken up from power down state. wtis timeout interval selection t tis interrupt period t int wtr timeout interval (wdt_clk=12 mhz) min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.33 us ~ 86.67 us 001 2 6 * t wdt 1024 * t wdt 5.33 us ~ 90.67 us 010 2 8 * t wdt 1024 * t wdt 21.33 us ~ 106.67 us 011 2 10 * t wdt 1024 * t wdt 85.33 us ~ 170.67 us 100 2 12 * t wdt 1024 * t wdt 341.33 us ~ 426.67 us 101 2 14 * t wdt 1024 * t wdt 1.36 ms ~ 1.45 ms 110 2 16 * t wdt 1024 * t wdt 5.46 ms ~ 5.55 ms 111 2 18 * t wdt 1024 * t wdt 21.84 ms ~ 21.93 ms table 5-7 watchdog timeout interval selection numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 376 - revision v1.06 t tis rst int 1024 * t wdt 63 * t wdt minimum t wtr t int t rst maximum t wtr t wdt t wdt : watchdog engine clock time period t tis : watchdog timeout interval selection period t int : watchdog interrupt period t rst : watchdog reset period t wtr : watchdog timeout interval period figure 5-64 timing of interrupt and reset signal numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 377 - revision v1.06 5.11.2 features z 18-bit free running counter to avoid cpu from watchdog timer reset before the delay time expires. z selectable time-out interval (2^4 ~ 2^18) and the time out interval is 86.67 us ~ 21.93 ms (if wdt_clk = 12 mhz). z reset period = (1 / 12 mhz) * 63, if wdt_clk = 12 mhz. 5.11.3 block diagram the watchdog timer clock control and block diagram are shown as following. figure 5-65 watchdog timer clock control figure 5-66 watchdog timer block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 378 - revision v1.06 5.11.4 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value wdt_ba = 0x4000_4000 wtcr wdt_ba+0x00 r/w watchdog timer control register 0x0000_0700 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 379 - revision v1.06 5.11.5 register description watchdog timer control register (wtcr) register offset r/w description reset value wtcr wdt_ba+0x00 r/w watchdog timer control register 0x0000_0700 note: all bits can be write in this regist er are write-protected. to program it needs to write ?59h?, ?16h?, ?88h? to address 0x5000_0100 to disable register protection. referenc e the register regwrprot at address gcr_ba+0x100. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved wtis 7 6 5 4 3 2 1 0 wte wtie wtwkf wtwke wtif wtrf wtre wtr bits descriptions [31:11] reserved reserved [10:8] wtis watchdog timer interval select (write-protection bits) these three bits select the timeout interval for the watchdog timer. wtis timeout interval selection interrupt period wtr timeout interval (wdt_clk=12 mhz) 000 2 4 * t wdt (2 4 + 1024) * t wdt 1.33 us ~ 86.67 us 001 2 6 * t wdt (2 6 + 1024) * t wdt 5.33 us ~ 90.67 us 010 2 8 * t wdt (2 8 + 1024) * t wdt 21.33 us ~ 106.67 us 011 2 10 * t wdt (2 10 + 1024) * t wdt 85.33 us ~ 170.67 us 100 2 12 * t wdt (2 12 + 1024) * t wdt 341.33 us ~ 426.67 us 101 2 14 * t wdt (2 14 + 1024) * t wdt 1.36 ms ~ 1.45 ms 110 2 16 * t wdt (2 16 + 1024) * t wdt 5.46 ms ~ 5.55 ms 111 2 18 * t wdt (2 18 + 1024) * t wdt 21.84 ms ~ 21.93 ms [7] wte watchdog timer enable (write-protection bit) 0 = disable the watchdog timer (this ac tion will reset the internal counter) 1 = enable the watchdog timer [6] wtie watchdog timer interrupt enable (write-protection bit) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 380 - revision v1.06 0 = disable the watchdog timer interrupt 1 = enable the watchdog timer interrupt [5] wtwkf watchdog timer wakeup flag if watchdog timer causes cpu wakes up from power-down mode, this bit will be set to high. it must be cleared by software with a write 1 to this bit. 0 = watchdog timer does not cause cpu wakeup. 1 = cpu wake up from sleep or power-down mode by watchdog timeout. [4] wtwke watchdog timer wakeup function enable bit (write-protection bit) 0 = disable watchdog timer wakeup cpu function. 1 = enable the wakeup function that wa tchdog timer timeout can wake up cpu from power-down mode. note: chip can wakeup by wdt only if wdt clock source select rc10k [3] wtif watchdog timer interrupt flag if the watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the watchdog timer interrupt has occurred. 0 = watchdog timer interrupt did not occur 1 = watchdog timer interrupt occurs note:this bit is cleared by writing 1 to this bit. [2] wtrf watchdog timer reset flag when the watchdog timer initiates a reset, the hardware will set this bit. this flag can be read by software to determine the source of reset. software is responsible to clear it manually by writing 1 to it. if wtre is disabled, then the watchdog timer has no effect on this bit. 0 = watchdog timer reset did not occur 1 = watchdog timer reset occurs note: this bit is cleared by writing 1 to this bit. [1] wtre watchdog timer reset enable (write-protection bit) setting this bit will enable the watchdog timer reset function. 0 = disable watchdog timer reset function 1 = enable watchdog timer reset function [0] wtr clear watchdog timer (write-protection bit) set this bit will clear the watchdog timer. 0 = writing 0 to this bit has no effect 1 = reset the contents of the watchdog timer note: this bit will auto clear after few clock cycle numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 381 - revision v1.06 5.12 uart interface controller (uart) numicro ? nuc100 medium density provides up to three channels of universal asynchronous receiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart, besides, only uart0 and uart1 support flow control function. numicro ? nuc100 low density only supports uart0 and uart1. 5.12.1 overview the universal asynchronous receiver/transmitter (uart) performs a serial-to-parallel conversion on data received from the periphera l, and a parallel-to-serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function, lin master/slave mode function and rs-485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (parity error or framing error or break interrupt) (int_rls), receiver buffer time out interrupt (int_tout), modem/wakeup status interrupt (int_modem), buffer error interrupt (int_buf_err) and lin receiver break field detected interrupt (int_lin_rx_break). interr upts of uart0 and uart2 share the interrupt number 12 (vector number is 28); interrupt number 13 (vector number is 29) only supports uart1 interrupt. refer to nested vectored interrupt controller chapter for system interrupt map. the uart0 is built-in with a 64-byte transmitter fifo (tx_fifo) and a 64-byte receiver fifo (rx_fifo) that reduces the number of interrupt s presented to the cpu and the uart1~2 are equipped 16-byte transmitter fifo (tx_fifo) and 16 -byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any time dur ing the operation. the reported status information includes the type and condition of the transfer op erations being performed by the uart, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. the uart includes a prog rammable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). table 5-8 lists the equations in the various conditions and table 5-9 list the uart baud rate setting table. mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 5-8 uart baud rate equation system clock = 22.1184mhz mode0 mode1 mode2 baud rate parameter register parameter register parameter register 921600 x x a=0,b=11 0x2b00_0000 a=22 0x3000_0016 460800 a=1 0x0000_0001 a=1,b=15 a=2,b=11 0x2f00_0001 0x2b00_0002 a=46 0x3000_002e numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 382 - revision v1.06 230400 a=4 0x0000_0004 a=4,b=15 a=6,b=11 0x2f00_0004 0x2b00_0006 a=94 0x3000_005e 115200 a=10 0x0000_000a a=10,b=15 a=14,b=11 0x2f00_000a 0x2b00_000e a=190 0x3000_00be 57600 a=22 0x0000_0016 a=22,b=15 a=30,b=11 0x2f00_0016 0x2b00_001e a=382 0x3000_017e 38400 a=34 0x0000_0022 a=62,b=8 a=46,b=11 a=34,b=15 0x2800_003e 0x2b00_002e 0x2f00_0022 a=574 0x3000_023e 19200 a=70 0x0000_0046 a=126,b=8 a=94,b=11 a=70,b=15 0x2800_007e 0x2b00_005e 0x2f00_0046 a=1150 0x3000_047e 9600 a=142 0x0000_008e a=254,b=8 a=190,b=11 a=142,b=15 0x2800_00fe 0x2b00_00be 0x2f00_008e a=2302 0x3000_08fe 4800 a=286 0x0000_011e a=510,b=8 a=382,b=11 a=286,b=15 0x2800_01fe 0x2b00_017e 0x2f00_011e a=4606 0x3000_11fe table 5-9 uart baud rate setting table the uart0 and uart1 controllers support auto-flow control function that uses two low-level signals, /cts (clear-to-send) and /rts (request- to-send), to control the flow of data transfer between the uart and external devices (ex: mode m). when auto-flow is enabled, the uart is not allowed to receive data until the uart asserts /rts to external device. when the number of bytes in the rx fifo equals the value of rt s_tri_lev (ua_fcr [19:16]), the /rts is de- asserted. the uart sends data out when uart controller detects /cts is asserted from external device. if a valid asserted /cts is not detect ed the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) f unction (user must set irda_en (ua_fun_sel [1]) to enable irda function ). the sir specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex ). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half-duplex only. so it cannot transmit and receive data at the same time. the irda sir phy sical layer specifies a minimum 10ms transfer delay between transmission and reception. this del ay feature must be implemented by software. the alternate function of uart controllers is lin (local interconnect network) function. the lin mode is selected by setting the lin_en bit in ua _fun_sel register. in lin mode, one start bit and 8-bit data format with 1-bit stop bit are r equired in accordance with the lin standard. for numicro ? nuc100 low density, another alternate function of uart controllers is rs-485 9 bit mode function, and direction control provided by rts pin or can program gpio (pb.2 for rts0 and pb.6 for rts1) to implement the function by software. the rs-485 mode is selected by setting the ua_fun_sel register to select rs-485 function. the rs-485 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. in rs-485 mode, many characteristics of the rx and tx are same as uart. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 383 - revision v1.06 5.12.2 features z full duplex, asynchronous communications z separate receive / transmit 64/16/16 bytes (u art0/uart1/uart2) entry fifo for data payloads z support hardware auto flow control/flow control function (cts, rts) and programmable rts flow control trigger level (uart0 and uart1 support) z programmable receiver buffer trigger level z support programmable baud-rate generator for each channel individually z support cts wake up function (uart0 and uart1 support) z support 7 bit receiver buffer time out detection function z uart0/uart1 can be served by the dma controller z programmable transmitting data delay time bet ween the last stop and the next start bit by setting ua_tor [dly] register z support break error, frame error, parity erro r and receive / transmit buffer overflow detect function z fully programmable serial-interface characteristics ? programmable number of data bit, 5, 6, 7, 8 bit character ? programmable parity bit, even, odd, no par ity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation z support irda sir function mode ? support for 3/16 bit duration for normal mode z support lin function mode ? support lin master/slave mode ? support programmable break generation function for transmitter ? support break detect function for receiver z support rs-485 function mode. (low density only) ? support rs-485 9bit mode ? support hardware or software direct enable control provided by rts pin numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 384 - revision v1.06 5.12.3 block diagram the uart clock control and block diagram are shown as figure 5-67 and figure 5-68. figure 5-67 uart clock control diagram figure 5-68 uart block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 385 - revision v1.06 tx_fifo the transmitter is buffered with a 64/16 byte fifo to reduce the number of interrupts presented to the cpu. rx_fifo the receiver is buffered with a 64/16 byte fifo (plus three error bits per byte) to reduce the number of interrupts presented to the cpu. tx shift register this block is the shifting the transmitting data out serially control block. rx shift register this block is the shifting the receiving data in serially control block. modem control register this register controls the interface to the modem or data set (or a peripheral device emulating a modem). baud rate generator divide the external clock by the divisor to get the desired baud rate clock. refer to baud rate equation. irda encode this block is irda encode control block. irda decode this block is irda decode control block. control and status register this field is register set that including the fifo control registers (ua_fcr), fifo status registers (ua_fsr), and line control register (ua_lcr) for transmitter and receiver. the time out control register (ua_tor) identifies the condition of time out interrupt. this register set also includes the interrupt enable register (ua_ier) and interrupt st atus register (ua_isr) to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt. there are seven types of interrupts, transmitter fifo empty inte rrupt(int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (par ity error or framing error or break interrupt) (int_rls) , time out interrupt (int_tout), modem/wakeup status interrupt (int_modem), buffer error interrupt (int_buf_err) and lin receiver break field detected interrupt (int_lin_rx_break). numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 386 - revision v1.06 the following diagram demonstrates the auto-flow control block diagram. tx fifo parallel to serial tx /cts flow control rx fifo serial to parallel rx /rts flow control apb bus note: only supported in uart0 and uart1 figure 5-69 auto flow control block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 387 - revision v1.06 5.12.4 irda mode the uart supports irda sir (serial infrared) tr ansmit encoder and receive decoder, and irda mode is selected by setting the irda_en bit in ua_fun_sel register. when in irda mode, the ua_baud [d iv_x_en] register must disable. baud rate = clock / (16 * brd) , where brd is baud rate divider in ua_baud register. the following diagram demonstrates the irda control block diagram. uart tx rx irda sir ir_sout ir_sin sout sin ir transceiver emit infra red ray detect infra red ray ircr baudout irda_enable tx_select int_tx inv_rx tx pin rx pin figure 5-70 irda block diagram 5.12.4.1 irda sir transmit encoder the irda sir tran smit encoder modulate non-re turn-to zero (nrz) transmit bit stream output from uart. the irda sir physical layer spec ifies use of return-to-zero, inverted (rzi) modulation scheme which represent logic 0 as an infra light pulse. the modulated output pulse stream is transmitted to an external output driver and infrared light emitting diode. in normal mode, the transmitted pulse width is specified as 3/16 period of baud rate. 5.12.4.2 irda sir receive decoder the irda sir receive de coder demodulates the retu rn-to-zero bit stream from the input detector and outputs the nrz serial bits stream to the uart received data input. the decoder input is normally high in the idle state. (because of th is, ircr bit 6 should be set as 1 by default) a start bit is detected when the decoder input is low 5.12.4.3 irda sir operation the irda sir enco der/decoder provides functiona lity which converts between uart data stream and half duplex serial sir interface. the following diagram is irda encoder/decoder waveform: numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 388 - revision v1.06 sout (from uart tx) ir_sout (encoder output) ir_sin (decorder input) sin (to uart rx) 0010111001 1 010010100 1 1 bit pulse width 3/16 bit width 3/16 bit width stop bit start bit start bit stop bit tx timing rx timing figure 5-71 irda tx/rx timing diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 389 - revision v1.06 5.12.5 lin (local interconnection network) mode the uart supports lin function, and lin mode is selected by setting the lin_en bit in ua_fun_sel register. in lin mode, each byte field is initialed by a start bit with value zero (dominant), followed by 8 data bits (lsb is first) and ended by 1 stop bit with value one (recessive) in accordance with the lin standard. the following diagram is the structure of lin function mode: data 1 data 2 data n check sum protected identifier field header response space response inter- frame space frame frame slot synch field break field figure 5-72 structure of lin frame the program flow of lin bus transmit transfer (tx) is shown as following 1. setting the lin_en bit in ua_fun_sel register to enable lin bus mode. 2. fill ua_lin_bkfl in ua_lin_bcnt to choose break field length. (the break field length is ua_lin_bkfl + 2). 3. fill 0x55 to ua_thr to request synch field transmission. 4. request identifier field transmission by wr iting the protected identifier value in the ua_thr 5. setting the lin_tx_en bit in ua_lin_bcnt r egister to start transmission (when break filed operation is finished, lin_tx_en will be cleared automatically). 6. when the stop bit of the last byte thr has been sent to bus, hardware will set flag te_flag in ua_fsr to 1. 7. fill n bytes data and checksum to ua_thr then repeat step 5 and 6 to transmit the data. the program flow of lin bus receiver transfer (rx) is show as following 1. setting the lin_en bit in ua_fun_sel register to enable lin bus mode. 2. setting the lin_rx_en bit in ua_lin_ bcnt register to enable lin rx mode. 3. waiting for the flag lin_rx_break_if in ua_isr to ch eck rx received break field or not. 4. waiting for the flag rda_if in ua_isr and read back the ur_rbr register. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 390 - revision v1.06 5.12.6 rs-485 function mode (low density only) the uart support rs-485 9 bit mode function . the rs-485 mode is selected by setting the ua_fun_sel register to select rs-485 function. the rs-485 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. in rs-485 mode, many characteristics of the rx and tx are same as uart. when in rs-485 mode, the controller can configuration of it as an rs -485 addressable slave and the rs-485 master transmitter will identi fy an address character by setting the parity (9 th bit) to 1. for data characters, the parity is set to 0. softwa re can use ua_lcr register to control the 9-th bit (when the pbe , epe and spe are set, the 9-th bit is transmitted 0 and when pbe and spe are set and epe is cleared, the 9-th bit is transmitted 1). the controller support three operation mode that is rs-485 normal multidrop operation mode (nmm), rs-485 auto address detection operation mode (aad) and rs-485 auto directi on control operation mode (aud), software can choose any operation mode by programming ua_rs-485_csr register, and software can driving the transfer delay time between the last stop bit leaving the tx-fifo and the de-assertion of by setting ua_tor [dly] register. rs-485 normal multidrop operation mode (nmm) in rs-485 normal multidrop operation mode, in first, software must decided the data which before the address byte be detected will be stored in rx-fifo or not. if software want to ignore any data before address byte detected, the flow is set uart_fcr[rs485_rx_dis] then enable ua_rs-485[rs485_nmm] and the receiver will ignore any data until an address byte is detected (bit9 =1) and the address byte data will be stored in the rx-fifo. if software wants to receive any data before address byte detected, the flow is disable uart_fcr [rs485_rx_dis] then enable ua_rs-485[rs485_nmm] and the receiver will rece ived any data. if an address byte is detected (bit9 =1), it will generator an interrupt to cpu and software can decide whether enable or disable receiver to accept the following data byte by setting ua_rs-485_csr [rx_dis]. if the receiver is be enabled, all received byte data will be accepted and stored in the rx-fifo, and if the receiver is disabled, all received byte data will be i gnore until the next address byte be detected. if software disable receiver by setting ua_rs-4 85_csr [rx_dis] register, when a next address byte be detected, the controller will clear the ua _rs-485_csr [rx_dis] bit and the address byte data will be stored in the rx-fifo. rs-485 auto address detection operation mode (aad) in rs-485 auto address detection operation mode, the receiver will ignore any data until an address byte is detected (bit9 =1) and the address byte data match the ua_rs- 485[addr_match] value. the address byte data will be stored in the rx-fifo. the all received byte data will be accepted and stored in the rx -fifo until and address byte data not match the ua_rs-485[addr_match] value. rs-485 auto direction mode (aud) another option function of rs-485 controllers is rs-485 auto direction control function . the rs-485 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. the rts line is connected to the rs-485 driver enable such that setting the rts line to high (logic 1) enables the rs-485 driver. setting the rts line to low (logic 0) puts the driver into the tri-state condi tion. user can setting lev_rts in ua_mcr register to change the rts driving level. program sequence example: 1. program fun_sel in ua_fun_sel to select rs-485 function. 2. program the rx_dis bit in ua_fcr regi ster to determine enable or disable rs-485 receiver numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 391 - revision v1.06 3. program the rs-485_nmm or rs-485_aad mode. 4. if the rs-485_aad mode is selected , the addr_match is programmed for auto address match value. 5. determine auto direction cont rol by programming rs-485_aud. figure 5-73 structure of rs-485 frame numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 392 - revision v1.06 5.12.7 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value uart base address : channel0 : uart0_ba (high speed) = 0x4005_0000 channel1 : uart1_ba (normal speed)= 0x4015_0000 channel2 : uart2_ba (normal speed)= 0x4015_4000 uart0_ba+0x00 r uart0 receive buffer register undefined uart1_ba+0x00 r uart1 receive buffer register undefined ua_rbr uart2_ba+0x00 r uart2 receive buffer register undefined uart0_ba+0x00 w uart0 transmit holding register undefined uart1_ba+0x00 w uart1 transmit holding register undefined ua_thr uart2_ba+0x00 w uart2 transmit holding register undefined uart0_ba+0x04 r/w uart0 interrupt enable register 0x0000_0000 uart1_ba+0x04 r/w uart1 interrupt enable register 0x0000_0000 ua_ier uart2_ba+0x04 r/w uart2 interrupt enable register 0x0000_0000 uart0_ba+0x08 r/w uart0 fifo control register 0x0000_0000 uart1_ba+0x08 r/w uart1 fifo control register 0x0000_0000 ua_fcr uart2_ba+0x08 r/w uart2 fifo control register 0x0000_0000 uart0_ba+0x0c r/w uart0 line control register 0x0000_0000 uart1_ba+0x0c r/w uart1 line control register 0x0000_0000 ua_lcr uart2_ba+0x0c r/w uart2 line control register 0x0000_0000 uart0_ba+0x10 r/w uart0 modem control register 0x0000_0000 uart1_ba+0x10 r/w uart1 modem control register 0x0000_0000 ua_mcr uart2_ba+0x10 r/w reserved 0x0000_0000 uart0_ba+0x14 r/w uart0 modem status register 0x0000_0000 uart1_ba+0x14 r/w uart1 modem status register 0x0000_0000 ua_msr uart2_ba+0x14 r/w reserved 0x0000_0000 uart0_ba+0x18 r/w uart0 fifo status register 0x1040_4000 uart1_ba+0x18 r/w uart1 fifo status register 0x1040_4000 ua_fsr uart2_ba+0x18 r/w uart2 fifo status register 0x1040_4000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 393 - revision v1.06 uart0_ba+0x1c r/w uart0 interrupt status register 0x0000_0002 uart1_ba+0x1c r/w uart1 interrupt status register 0x0000_0002 ua_isr uart2_ba+0x1c r/w uart2 interrupt status register 0x0000_0002 uart0_ba+0x20 r/w uart0 time out register 0x0000_0000 uart1_ba+0x20 r/w uart1 time out register 0x0000_0000 ua_tor uart2_ba+0x20 r/w uart2 time out register 0x0000_0000 uart0_ba+0x24 r/w uart0 baud rate divisor register 0x0f00_0000 uart1_ba+0x24 r/w uart1 baud rate divisor register 0x0f00_0000 ua_baud uart2_ba+0x24 r/w uart2 baud rate divisor register 0x0f00_0000 uart0_ba+0x28 r/w uart0 irda control register 0x0000_0040 uart1_ba+0x28 r/w uart1 irda control register 0x0000_0040 ua_ircr uart2_ba+0x28 r/w uart2 irda control register 0x0000_0040 uart0_ba+0x2c r/w uart0 alternate control/status register 0x0000_0000 uart1_ba+0x2c r/w uart1 alternate control/status register 0x0000_0000 ua_alt_csr uart2_ba+0x2c r/w uart2 alternate control/status register 0x0000_0000 uart0_ba+0x30 r/w uart0 function select register 0x0000_0000 uart1_ba+0x30 r/w uart1 function select register 0x0000_0000 ua_fun_sel uart2_ba+0x30 r/w uart2 function select register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 394 - revision v1.06 5.12.8 register description receive buffer register (ua_rbr) register offset r/w description reset value uart0_ba+0x00 r uart0 receive buffer register undefined uart1_ba+0x00 r uart1 receive buffer register undefined ua_rbr uart2_ba+0x00 r uart2 receive buffer register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rbr bits descriptions [31:8] reserved reserved [7:0] rbr receive buffer register (read only) by reading this register, the uart will retu rn an 8-bit data received from rx pin (lsb first). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 395 - revision v1.06 transmit holding register (ua_thr) register offset r/w description reset value uart0_ba+0x00 w uart0 transmit holding register undefined uart1_ba+0x00 w uart1 transmit holding register undefined ua_thr uart2_ba+0x00 w uart2 transmit holding register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 thr bits descriptions [31:8] reserved reserved [7:0] thr transmit holding register by writing to this register, the uart will send out an 8-bit data through the tx pin (lsb first). numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 396 - revision v1.06 interrupt enable register (ua_ier) register offset r/w description reset value uart0_ba+0x04 r/w uart0 interrupt enable register 0x0000_0000 uart1_ba+0x04 r/w uart1 interrupt enable register 0x0000_0000 ua_ier uart2_ba+0x04 r/w uart2 interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 dma_rx_en dma_tx_en auto_cts_ en auto_rts_ en time_out_e n reserved lin_rx_brk _ien 7 6 5 4 3 2 1 0 reserved wake_en buf_err_ie n rto_ien modem_ien rls_ien thre_ien rda_ien bits descriptions [31:16] reserved reserved [15] dma_rx_en rx dma enable (not available in uart2 channel) this bit can enable or di sable rx dma service. 1 = enable rx dma 0 = disable rx dma [14] dma_tx_en tx dma enable (not available in uart2 channel) this bit can enable or di sable tx dma service. 1 = enable tx dma 0 = disable tx dma [13] auto_cts_en cts auto flow control enable (not available in uart2 channel) 1 = enable cts auto flow control 0 = disable cts auto flow control when cts auto-flow is enabled, the uart will send data to external device when cts input assert (uart will not send data to device until cts is asserted). [12] auto_rts_en rts auto flow control enable (not available in uart2 channel) 1 = enable rts auto flow control 0 = disable rts auto flow control when rts auto-flow is enabled, if the number of bytes in the rx fifo equals the ua_fcr [rts_tri_lev], the uart will de-assert rts signal. [11] time_out_en time out counter enable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 397 - revision v1.06 1 = enable time-out counter 0 = disable time-out counter [10:9] reserved reserved [8] lin_rx_brk_ien lin rx break field detected interrupt enable 1 = enable lin bus rx break filed interrupt 0 = mask off lin bus rx break filed interrupt note: this field is used for lin function mode. [7] reserved reserved [6] wake_en wake up cpu function enable (not available in uart2 channel) 0 = disable uart wake up cpu function 1 = enable wake up function, when the system is in deep sleep mode, an external cts change will wake up cpu from deep sleep mode. [5] buf_err_ien buffer error interrupt enable 1 = enable int_buf_err 0 = mask off int_buf_err [4] rto_ien rx time out interrupt enable 1 = enable int_tout 0 = mask off int_tout [3] modem_ien modem status interrupt enable (not available in uart2 channel) 1 = enable int_modem 0 = mask off int_modem [2] rls_ien receive line status interrupt enable 1 = enable int_rls 0 = mask off int_rls [1] thre_ien transmit holding register empty interrupt enable 1 = enable int_thre 0 = mask off int_thre [0] rda_ien receive data available interrupt enable . 1 = enable int_rda 0 = mask off int_rda numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 398 - revision v1.06 fifo control register (ua_fcr) register offset r/w description reset value uart0_ba+0x08 r/w uart0 fifo control register 0x0000_0000 uart1_ba+0x08 r/w uart1 fifo control register 0x0000_0000 ua_fcr uart2_ba+0x08 r/w uart2 fifo control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved rts_tri_lev 15 14 13 12 11 10 9 8 reserved rx_dis 7 6 5 4 3 2 1 0 rfitl reserved tfr rfr reserved bits descriptions [31:20] reserved reserved [19:16] rts_tri_lev rts trigger level for auto-flow control use (not available in uart2 channel) rts_tri_lev trigger level (bytes) 0000 01 0001 04 0010 08 0011 14 0100 30/14 (high speed/normal speed) 0101 46/14 (high speed/normal speed) 0110 62/14 (high speed/normal speed) others 62/14 (high speed/normal speed) note: this field is used for auto rts flow control. [15:9] reserved reserved [8] rx_dis receiver disable register. the receiver is disabled or not (set 1 is disable receiver) 1 = disable receiver 0 = enable receiver note: this field is used for rs-485 normal multi-drop mode. it should be programmed before ua_alt_csr [rs-485_nmm] is programmed. [7:4] rfitl rx fifo interrupt (int_rda) trigger level numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 399 - revision v1.06 when the number of bytes in the receive fifo equals the rfitl then the rda_if will be set (if ua_ier [rda_ien] is enable, an interrupt will generated). rfitl intr_rda trigger level (bytes) 0000 01 0001 04 0010 08 0011 14 0100 30/14 (high speed/normal speed) 0101 46/14 (high speed/normal speed) 0110 62/14 (high speed/normal speed) others 62/14 (high speed/normal speed) [3] reserved reserved [2] tfr tx field software reset when tx_rst is set, all the byte in the tr ansmit fifo and tx internal state machine are cleared. 1 = writing 1 to this bit will reset the tx internal state machine and pointers. 0 = writing 0 to this bit has no effect. note: this bit will auto clear needs at least 3 uart engine clock cycles. [1] rfr rx field software reset when rx_rst is set, all the byte in the re ceiver fifo and rx internal state machine are cleared. 1 = writing 1 to this bit will reset the rx internal state machine and pointers. 0 = writing 0 to this bit has no effect. note: this bit will auto clear needs at least 3 uart engine clock cycles. [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 400 - revision v1.06 line control register (ua_lcr) register offset r/w description reset value uart0_ba+0x0c r/w uart0 line control register 0x0000_0000 uart1_ba+0x0c r/w uart1 line control register 0x0000_0000 ua_lcr uart2_ba+0x0c r/w uart2 line control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bcb spe epe pbe nsb wls bits descriptions [31:7] reserved reserved [6] bcb break control bit when this bit is set to logic 1, the serial data output (tx) is forced to the spacing state (logic 0). this bit acts only on tx and has no effect on the transmitter logic. [5] spe stick parity enable 1 = when bits pbe , epe and spe are set, the parity bit is transmitted and checked as cleared. when pbe and spe are set and epe is cleared, the parity bit is transmitted and checked as set. 0 = disable stick parity [4] epe even parity enable 1 = even number of logic 1?s are transmitted or checked in the data word and parity bits. 0 = odd number of logic 1?s are transmitted or checked in the data word and parity bits. this bit has effect only when bit 3 (parity bit enable) is set. [3] pbe parity bit enable 1 = parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. 0 = parity bit is not generated (transmit data) or checked (receive data) during transfer. [2] nsb number of ?stop bit? 1= one and a half ? stop bit? is generated in the transmitted data when 5-bit word length is selected; 0= one ? stop bit? is generated in the transmitted data two ?stop bit? is generated when 6-, 7- and 8-bit word length is selected. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 401 - revision v1.06 [1:0] wls word length select wls[1:0] character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 402 - revision v1.06 modem control register (ua_mcr) (not available in uart2 channel) register offset r/w description reset value uart0_ba+0x10 r/w uart0 modem control register 0x0000_0000 uart1_ba+0x10 r/w uart1 modem control register 0x0000_0000 ua_mcr uart2_ba+0x10 r/w reserved 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved rts_st reserved lev_rts reserved 7 6 5 4 3 2 1 0 reserved rts reserved bits descriptions [31:14] reserved reserved [13] rts_st rts pin state (read only) (not available in uart2 channel) this bit is the output pin status of rts. [12:10] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 403 - revision v1.06 [9] lev_rts rts trigger level (not available in uart2 channel) this bit can change the rts trigger level. 1= high level triggered 0= low level triggered [8:2] reserved reserved [1] rts rts (request-to-send) signal (not available in uart2 channel) 0 = drive rts pin to logic 1 (if the lev_rts set to low level triggered). 1 = drive rts pin to logic 0 (if the lev_rts set to low level triggered). 0 = drive rts pin to logic 0 (if the lev_rts set to high level triggered). 1 = drive rts pin to logic 1 (if the lev_rts set to high level triggered). [0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 404 - revision v1.06 modem status register (ua_msr) (not available in uart2 channel) register offset r/w description reset value uart0_ba+0x14 r/w uart0 modem status register 0x0000_0000 uart1_ba+0x14 r/w uart1 modem status register 0x0000_0000 ua_msr uart2_ba+0x14 r/w reserved 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved lev_cts 7 6 5 4 3 2 1 0 reserved cts_st reserved dctsf bits descriptions [31:9] reserved reserved [8] lev_cts cts trigger level (not available in uart2 channel) this bit can change the cts trigger level. 1= high level triggered 0= low level triggered [7:5] reserved reserved [4] cts_st cts pin status (read only) (not available in uart2 channel) this bit is the pin status of cts. [3:1] reserved reserved [0] dctsf detect cts state change flag (read only) (not available in uart2 channel) this bit is set whenever cts input has change state, and it will generate modem interrupt to cpu when ua_ier [modem_ien] is set to 1. software can write 1 to clear this bit to zero numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 405 - revision v1.06 fifo status register (ua_fsr) register offset r/w description reset value uart0_ba+0x18 r/w uart0 fifo status register 0x1040_4000 uart1_ba+0x18 r/w uart1 fifo status register 0x1040_4000 ua_fsr uart2_ba+0x18 r/w uart2 fifo status register 0x1040_4000 31 30 29 28 27 26 25 24 reserved te_flag reserved tx_over_if 23 22 21 20 19 18 17 16 tx_full tx_empty tx_pointer 15 14 13 12 11 10 9 8 rx_full rx_empty rx_pointer 7 6 5 4 3 2 1 0 reserved bif fef pef rs485_add_ detf reserved rx_over_if bits descriptions [31:29] reserved reserved [28] te_flag transmitter empty flag (read only) bit is set by hardware when tx fifo (ua_thr) is empty and the stop bit of the last byte has been transmitted. bit is cleared automatically when tx fifo is not empty or the last byte transmission has not completed. [27:25] reserved reserved [24] tx_over_if tx overflow error interrupt flag (read only) if tx fifo (ua_thr) is full, an additional wr ite to ua_thr will cause this bit to logic 1. note: this bit is read only, but can be cleared by writing ?1? to it. [23] tx_full transmitter fifo full (read only) this bit indicates tx fifo full or not. this bit is set when tx_pointer is equal to 64/16(uart0/uart1), otherwise is cleared by hardware. [22] tx_empty transmitter fifo empty (read only) this bit indicates tx fifo empty or not. when the last byte of tx fifo has been transferred to transmitter shift register, hardware sets this bit high. it will be clear ed when writing data into thr (tx fifo not empty). [21:16] tx_pointer tx fifo pointer (read only) this field indicates the tx fifo buffer pointer. when cpu writes one byte into ua_thr, tx_pointer increases one. when one byte of tx fifo is transferred to numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 406 - revision v1.06 transmitter shift register, tx_pointer decreases one. [15] rx_full receiver fifo full (read only) this bit initiates rx fifo full or not. this bit is set when rx_pointer is equal to 64/16(uart0/uart1), otherwise is cleared by hardware. [14] rx_empty receiver fifo empty (read only) this bit initiate rx fifo empty or not. when the last byte of rx fifo has been read by cpu, hardware sets this bit high. it will be cleared when uart receives any new data. [13:8] rx_pointer rx fifo pointer (read only) this field indicates the rx fifo buffer po inter. when uart receives one byte from external device, rx_pointer increases one. when one byte of rx fifo is read by cpu, rx_pointer decreases one. [7] reserved reserved [6] bif break interrupt flag (read only) this bit is set to a logic 1 whenever t he received data input(rx) is held in the ?spacing state? (logic 0) for longer than a fu ll word transmission time (that is, the total time of ?start bit? + data bits + parit y + stop bits) and is reset whenever the cpu writes 1 to this bit. note: this bit is read only, but can be cleared by writing ?1? to it. [5] fef framing error flag (read only) this bit is set to logic 1 whenever the rec eived character does not have a valid ?stop bit? (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the cpu writes 1 to this bit. note: this bit is read only, but can be cleared by writing ?1? to it. [4] pef parity error flag (read only) this bit is set to logic 1 whenever the received character does not have a valid ?parity bit?, and is reset whenever the cpu writes 1 to this bit. note: this bit is read only, but can be cleared by writing ?1? to it. [3] rs485_add_detf rs-485 address byte detection flag (read only) (low density only) this bit is set to logic 1 and set ua_a lt_csr [rs-485_add_en] whenever in rs- 485 mode the receiver detect any address byte received address byte character (bit9 = ?1?) bit", and it is reset whenever the cpu writes 1 to this bit. note: this field is used for rs-485 function mode. note: this bit is read only, but can be cleared by writing ?1? to it. [2:1] reserved reserved [0] rx_over_if rx overflow error if (read only) this bit is set when rx fifo overflow. if the number of bytes of received data is greater than rx_fifo (ua_rbr) size, 64/16 bytes of uart0/uart1, this bit will be set. note: this bit is read only, but can be cleared by writing ?1? to it. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 407 - revision v1.06 interrupt status contro l register (ua_isr) register offset r/w description reset value uart0_ba+0x1c r/w uart0 interrupt status register 0x0000_0002 uart1_ba+0x1c r/w uart1 interrupt status register 0x0000_0002 ua_isr uart2_ba+0x1c r/w uart2 interrupt status register 0x0000_0002 31 30 29 28 27 26 25 24 hw_lin_rx_ break_int reserved hw_buf_er r_int hw_tout_i nt hw_modem _int hw_rls_int reserved 23 22 21 20 19 18 17 16 hw_lin_rx_ break_if reserved hw_buf_er r_if hw_tout_if hw_modem _if hw_rls_if reserved 15 14 13 12 11 10 9 8 lin_rx_bre ak_int reserved buf_err_in t tout_int modem_int rls_int thre_int rda_int 7 6 5 4 3 2 1 0 lin_rx_bre ak_if reserved buf_err_if tout_if modem_if rls_if thre_if rda_if bits descriptions [31] hw_lin_rx_br eak_int in dma mode, lin bus rx break field detected interrupt indicator (read only) this bit is set if lin_rx_brk_ien and hw_lin_rx_break_if are both set to 1. 1 = the lin rx break interrupt is generated in dma mode 0 = no lin rx break interrupt is generated in dma mode [30] reserved reserved [29] hw_buf_err_i nt in dma mode, buffer error interrupt indicator (read only) this bit is set if buf_err_ien and hw_buf_err_if are both set to 1. 1 = the buffer error interrupt is generated in dma mode 0 = no buffer error interrupt is generated in dma mode [28] hw_tout_int in dma mode, time out interrupt indicator (read only) this bit is set if tout_ien and hw_tout_if are both set to 1. 1 = the tout interrupt is generated in dma mode 0 = no tout interrupt is generated in dma mode [27] hw_modem_int in dma mode, modem status interrupt indicator (read only) (not available in uart2 channel) this bit is set if modem_ien and hw_modem_if are both set to 1. 1 = the modem interrupt is generated in dma mode 0 = no modem interrupt is generated in dma mode [26] hw_rls_int in dma mode, receive line status interrupt indicator (read only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 408 - revision v1.06 this bit is set if rls_ien and hw_rls_if are both set to 1. 1 = the rls interrupt is generated in dma mode 0 = no rls interrupt is generated in dma mode [25:24] reserved reserved [23] hw_lin_rx_br eak_if in dma mode, lin bus rx break field detect interrupt flag (read only) this bit is set when rx received lin break field. if ua_ier [lin_rx_brk_ien] is enabled the lin rx break interrupt will be generated. note: this bit is read only, but can be cleared by writing ?1? to ua_isr [7]. [22] reserved reserved [21] hw_buf_err_i f in dma mode, buffer error interrupt flag (read only) this bit is set when the tx or rx fifo overflows (tx_over_if or rx_over_if is set). when buf_err_if is set, the transfer maybe is not correct. if ua_ier [buf_err_ien] is enabled, the buffer error interrupt will be generated. note: this bit is cleared when both tx_over_if and rx_over_if are cleared. [20] hw_tout_if in dma mode, time out interrupt flag (read only) this bit is set when the rx fifo is not empty and no activities occurred in the rx fifo and the time out counter equal to toic. if ua_ier [tout_ien] is enabled, the tout interrupt will be generated. note: this bit is read only and user can r ead ua_rbr (rx is in active) to clear it. [19] hw_modem_if in dma mode, modem interrupt flag (read only) (not available in uart2 channel) this bit is set when the cts pin has state change (dctsf=1). if ua_ier [modem_ien] is enabled, the modem interrupt will be generated. note: this bit is read only and reset to 0 when bit dctsf is cleared by a write 1 on dctsf. [18] hw_rls_if in dma mode, receive line status flag (read only) (low density only) this bit is set when the rx receive data have parity error, framing error or break error (at least one of 3 bits, bif, fef and pef, is set). if ua_ier [rls_ien] is enabled, the rls interrupt will be generated. note: when in rs-485 function mode, this field include ?receiver detect any address byte received address byte character (bit9 = ?1?) bit". note: this bit is read only and reset to 0 when all bits of bif, fef and pef are cleared. [17:16] reserved reserved [15] lin_rx_break_ int lin bus rx break field detected interrupt indicator (read only) this bit is set if lin_rx_brk_ien and lin_rx_break_if are both set to 1. 1 = the lin rx break interrupt is generated 0 = no lin rx break interrupt is generated [14] reserved reserved [13] buf_err_int buffer error interrupt indicator (read only) this bit is set if buf_err_ien and buf_err_if are both set to 1. 1 = the buffer error interrupt is generated 0 = no buffer error interrupt is generated [12] tout_int time out interrupt indicator (read only) this bit is set if tout_ien and tout_if are both set to 1. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 409 - revision v1.06 1 = the tout interrupt is generated 0 = no tout interrupt is generated [11] modem_int modem status interrupt indicator (read only). (not available in uart2 channel) this bit is set if modem_ien and modem_if are both set to 1. 1 = the modem interrupt is generated 0 = no modem interrupt is generated [10] rls_int receive line status interrupt indicator (read only). this bit is set if rls_ien and rls_if are both set to 1. 1 = the rls interrupt is generated 0 = no rls interrupt is generated [9] thre_int transmit holding register empty interrupt indicator (read only). this bit is set if thre_ien and thre_if are both set to 1. 1 = the thre interrupt is generated 0 = no thre interrupt is generated [8] rda_int receive data available interrupt indicator (read only). this bit is set if rda_ien and rda_if are both set to 1. 1 = the rda interrupt is generated 0 = no rda interrupt is generated [7] lin_rx_break_ if lin bus rx break field detected flag (read only) this bit is set when rx received lin break field. if ua_ier [lin_rx_brk_ien] is enabled the lin rx break interrupt will be generated. note: this bit is read only, but can be cleared by writing ?1? to it. [6] reserved reserved [5] buf_err_if buffer error interrupt flag (read only) this bit is set when the tx or rx fifo overflows (tx_over_if or rx_over_if is set). when buf_err_if is set, the transfer maybe is not correct. if ua_ier [buf_err_ien] is enabled, the buffer error interrupt will be generated. note: this bit is cleared when both tx_over_if and rx_over_if are cleared. [4] tout_if time out interrupt flag (read only) this bit is set when the rx fifo is not empty and no activities occurred in the rx fifo and the time out counter equal to toic. if ua_ier [tout_ien] is enabled, the tout interrupt will be generated. note: this bit is read only and user can r ead ua_rbr (rx is in active) to clear it. [3] modem_if modem interrupt flag (read only) (not available in uart2 channel) this bit is set when the cts pin has state change (dctsf=1). if ua_ier [modem_ien] is enabled, the modem interrupt will be generated. note: this bit is read only and reset to 0 when bit dctsf is cleared by a write 1 on dctsf. [2] rls_if receive line interrupt flag (read only). (low density only) this bit is set when the rx receive data have parity error, framing error or break error (at least one of 3 bits, bif, fef and pef, is set). if ua_ier [rls_ien] is enabled, the rls interrupt will be generated. note: when in rs-485 function mode, this field include ?receiver detect any address byte received address byte character (bit9 = ?1?) bit". numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 410 - revision v1.06 note: this bit is read only and reset to 0 when all bits of bif, fef and pef are cleared. [1] thre_if transmit holding register empty interrupt flag (read only). this bit is set when the last data of tx fifo is transferred to transmitter shift register. if ua_ier [thre_ien] is enabled, the thre interrupt will be generated. note: this bit is read only and it will be cleared when writing data into thr (tx fifo not empty). [0] rda_if receive data available interrupt flag (read only). when the number of bytes in the rx fifo equals the rfitl then the rda_if will be set. if ua_ier [rda_ien] is enabled, the rda interrupt will be generated. note: this bit is read only and it will be cleared when the number of unread bytes of rx fifo drops below the threshold level (rfitl). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 411 - revision v1.06 uart interrupt source interrupt enable bit interrupt indicator to interrupt controller interrupt flag flag cleared by lin rx break field detected interrupt lin_rx_brk_ien hw_lin_rx_break _int hw_lin_rx_brea k_if write ?1? to lin_rx_break_if buffer error interrupt int_buf_err buf_err_ien hw_buf_err_int hw_buf_err_if = (tx_over_if or rx_over_if) write ?1? to tx_over_if/ rx_over_if rx timeout interrupt int_tout rto_ien hw_tout_int hw_tout_if read ua_rbr modem status interrupt int_modem modem_ien hw_modem_int hw_modem_if = (dctsf) write ?1? to dctsf receive line status interrupt int_rls rls_ien hw_rls_int hw_rls_if = (bif or fef or pef or rs- 485_add_detf) write ?1? to bif/fef/pef/ rs- 485_add_detf transmit holding register empty interrupt int_thre thre_ien hw_thre_int hw_thre_if write ua_thr receive data available interrupt int_rda rda_ien hw_rda_int hw_rda_if read ua_rbr table 5-10 uart interrupt sources and flags table in dma mode (low density only) uart interrupt source interrupt enable bit interrupt indicator to interrupt controller interrupt flag flag cleared by lin rx break field detected interrupt lin_rx_brk_ien lin_rx_break_int lin_rx_break_if write ?1? to lin_rx_break_if buffer error interrupt int_buf_err buf_err_ien buf_err_int buf_err_if = (tx_over_if or rx_over_if) write ?1? to tx_over_if/ rx_over_if rx timeout interrupt int_tout rto_ien tout_int tout_if read ua_rbr modem status interrupt int_modem modem_ien modem_int modem_if = (dctsf) write ?1? to dctsf receive line status interrupt int_rls rls_ien rls_int rls_if = (bif or fef or pef) write ?1? to bif/fef/pef transmit holding register empty interrupt int_thre thre_ien thre_int thre_if write ua_thr receive data available interrupt int_rda rda_ien rda_int rda_if read ua_rbr table 5-11 uart interrupt sources and flags table in software mode numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 412 - revision v1.06 time out register (ua_tor) register offset r/w description reset value uart0_ba+0x20 r/w uart0 time out register 0x0000_0000 uart1_ba+0x20 r/w uart1 time out register 0x0000_0000 ua_tor uart2_ba+0x20 r/w uart2 time out register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 dly 7 6 5 4 3 2 1 0 reserved toic bits descriptions [31:16] reserved reserved [15:8] dly tx delay time value (low density only) this field is use to programming the transfe r delay time between the last stop bit and next start bit. [6:0] toic time out interrupt comparator the time out counter resets and starts counting (the counting clock = baud rate) whenever the rx fifo receives a new data word. once the content of time out counter (tout_cnt) is equal to that of time out interrupt comparator (toic), a receiver time out interrupt (int_tout) is generated if ua_ier [rto_ien]. a new incoming data word or rx fifo empty clears int_tout. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 413 - revision v1.06 baud rate divider register (ua_baud) register offset r/w description reset value uart0_ba+0x24 r/w uart0 baud rate divisor register 0x0f00_0000 uart1_ba+0x24 r/w uart1 baud rate divisor register 0x0f00_0000 ua_baud uart2_ba+0x24 r/w uart2 baud rate divisor register 0x0f00_0000 31 30 29 28 27 26 25 24 reserved div_x_en div_x_one divider_x 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 brd 7 6 5 4 3 2 1 0 brd bits descriptions [31:30] reserved reserved [29] div_x_en divider x enable the brd = baud rate divider, and the baud rate equation is baud rate = clock / [m * (brd + 2)]; the default value of m is 16. 1 = enable divider x (the equation of m = x+1, but divider_x [27:24] must >= 8). 0 = disable divider x (the equation of m = 16) refer to the table below for more information. note: when in irda mode, this bit must disable. [28] div_x_one divider x equal 1 1 = divider m = 1 (the equation of m = 1, but brd [15:0] must >= 3). 0 = divider m = x (the equation of m = x+1, but divider_x[27:24] must >= 8) refer to the table 5-12 below for more information. [27:24] divider_x divider x the baud rate divider m = x+1. [23:16] reserved reserved [15:0] brd baud rate divider the field indicated the baud rate divider numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 414 - revision v1.06 mode div_x_en div_x_one divider x brd baud rate equation 0 disable 0 b a uart_clk / [16 * (a+2)] 1 enable 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 enable 1 don?t care a uart_clk / (a+2), a must >=3 table 5-12 baud rate equation table numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 415 - revision v1.06 irda control register (ircr) register offset r/w description reset value uart0_ba+0x28 r/w uart0 irda control register 0x0000_0040 uart1_ba+0x28 r/w uart1 irda control register 0x0000_0040 ua_ircr uart2_ba+0x28 r/w uart2 irda control register 0x0000_0040 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved inv_rx inv_tx reserved tx_select reserved bits descriptions [31:7] reserved reserved [6] inv_rx inv_rx 1= inverse rx input signal 0= no inversion [5] inv_tx inv_tx 1= inverse tx output signal 0= no inversion [4:2] reserved reserved [1] tx_select tx_select 1= enable irda transmitter 0= enable irda receiver [0] reserved reserved note: when in irda mode, the ua_baud [div_x_en] regi ster must disable (the baud equation must be clock / 16 * (brd) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 416 - revision v1.06 uart alternate control/status register (ua_alt_csr) register offset r/w description reset value uart0_ba+0x2c r/w uart0 alternate control/status register 0x0000_0000 uart1_ba+0x2c r/w uart1 alternate control/status register 0x0000_0000 ua_alt_csr uart2_ba+0x2c r/w uart2 alternate control/status register 0x0000_0000 31 30 29 28 27 26 25 24 addr_match 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rs485_add_ en reserved rs485_aud rs485_aad rs485_nmm 7 6 5 4 3 2 1 0 lin_tx_en lin_rx_en reserved ua_lin_bkfl bits descriptions [31:24] addr_match address match value register (low density only) this field contains the rs-485 address match values. note: this field is used for rs -485 auto address detection mode. [23:16] reserved reserved [15] rs485_add_en rs-485 address detection enable (low density only) this bit is use to enable rs- 485 address detection mode. 1 = enable address detection mode 0 = disable address detection mode note: this field is used for rs-485 any operation mode. [14:11] reserved reserved [10] rs485_aud rs-485 auto direction mode (aud) (low density only) 1 = enable rs-485 auto direction operation mode (auo) 0 = disable rs-485 auto dire ction operation mode (auo) note: it can be active with rs-485_aad or rs-485_nmm operation mode. [9] rs485_aad rs-485 auto address detection operation mode (aad) (low density only) 1 = enable rs-485 auto address detection operation mode (aad) 0 = disable rs-485 auto address detection operation mode (aad) note: it can?t be active with rs-485_nmm operation mode. [8] rs485_nmm rs-485 normal multi-drop operation mode (nmm) (low density only) 1 = enable rs-485 normal multi-drop operation mode (nmm) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 417 - revision v1.06 0 = disable rs-485 normal multi-drop operation mode (nmm) note: it can?t be active with rs-485_aad operation mode. [7] lin_tx_en lin tx break mode enable 1 = enable lin tx break mode. 0 = disable lin tx break mode. note: when tx break field transfer operat ion finished, this bit will be cleared automatically. [6] lin_rx_en lin rx enable 1 = enable lin rx mode. 0 = disable lin rx mode. [5:4] reserved reserved [3:0] ua_lin_bkfl uart lin break field length this field indicates a 4-bi t lin tx break field count. note: this break field length is ua_lin_bkfl + 2 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 418 - revision v1.06 uart function select register (ua_fun_sel) register offset r/w description reset value uart0_ba+0x30 r/w uart0 function select register 0x0000_0000 uart1_ba+0x30 r/w uart1 function select register 0x0000_0000 ua_fun_sel uart2_ba+0x30 r/w uart2 function select register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved fun_sel bits descriptions [31:2] reserved reserved [1:0] fun_sel function select enable 00 = uart function 01 = enable lin function 10 = enable irda function 11 = enable rs-485 function (low density only) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 419 - revision v1.06 5.13 controller area network (can) 5.13.1 overview the controller area network (can) is a serial communications protocol which is multi-master and it efficiently supports distributed real-time control with very high level of security. its domain of application range from high speed networks to low cost multiplex wiring. in automotive electronics, engine control units, sensors, anti-ski d-systems, etc. are connected using can with bit-rates up to 1mbit/s. in can systems, a node does not make use of any information about the system configuration (station addresses). any nodes can be added to the can network without requiring any change in the software or hardware of any node. the information on the bus is sent in fixed format message of different but limited length. when t he bus is free, any connected unit may start to transmit a new message. the content of messa ge is named by identifier. the identifier does not indicate the destination of the message, but describes the meaning of the data, so that all nodes in the network are able to decide by message filtering whether the data is to be acted upon by them or not. within a can network it is guaranteed that a message is simultaneously accepted either by all nodes or by no node. 5.13.2 features z can 2.0b protocol compatibility z multi-master node z support 11-bit identifier as well as 29-bit identifier z bit rates up to 1mbits/s z nrz bit coding z error detection: bit error, stuff error, fo rm error, 15-bit crc detection, and acknowledge error z listen only mode (no acknowledge, no active error flags) z acceptance filter extensi on (4-byte code, 4-byte mask) z error interrupt for each can-bus error z extended receive buffer (8-byte fifo) z wakeup function numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 420 - revision v1.06 5.13.3 block diagram receive buffer transmit buffer acceptance filter bit stream processor register apb bus error management logic bit timing logic apb wrapper can tx can rx interrupt clock control pd.7 pd.6 can bus unit figure 5-74 can bus block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 421 - revision v1.06 5.13.4 functional description the bus has two complementary logical values, one is dominant bit represented by logic low level another is recessive bit represented by logic high level. 5.13.4.1 frame formats there are two different formats whi ch differ in the length of the identifier field: frames with the number of 11 bits identifier are denoted standa rd frames. in contras t, frames containing 29 bits identifier are denoted extended frames. 5.13.4.2 frame types messag e transfer is manifested and controlled by four different frame types: 1. a data frame carries data from a transmitter to the receivers 2. a remote data frame is transmitted by a bus unit to request the transmission of the data frame with the same identifier 3. an error frame is transmitted by any unit on detecting a bus error 4. an overload frame is used to provi de for an extra delay between the preceding and the succeeding data or remote frames data frames and remote frames can be us ed both in standard format and extended format; they are separated from prec eding frames by an interframe space. 5.13.4.3 data frame a data frame is com posed of seven different bit fields: start of frame, arbitration field, control field, crc filed, ack fiel d, and end of frame. the data field can be of length zero. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 422 - revision v1.06 figure 5-75 format of data frame 1 start of frame (standard format as well as extended format) the start of frame (sof) marks the beginning of data frames and remote frames. it consists of a single ?dominant? bit. a station is only allowed to start transmission when the bus is idle. all stations have to synchronize to leading edge caused by start of frame of the station starting transmission first. 2 arbitration field the format of arbitration field is different between standard format and extended format frames. in standard format, the arbitration field consists of 11 bit identifier and the rtr- bit. the identifier bits are denoted id-28? id-18. in extended format, the arbitration field cons ists of the 29 bit identifier, the srr- bit, the ide-bit, and the rtr-bit. the iden tifier bits are denoted id-28? id-0. note: in order to distinguish between standard format and extended format the reserved bit r1 is denoted as ide bit. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 423 - revision v1.06 figure 5-76 standard format in arbitration field figure 5-77 extended format in arbitration field 3 identifier a. standard format the identifier?s length is 11 bits and corresponds to the base id in extended format. these bits are transmitted in the order from id-28 to id-18. the least significant bit is id-18. the 7 most significant bits (id-28 ~ id-22) must not be all ?recessive? b. extended format in contrast to the standard format, the ext ended format consists of 29 bits. the format comprises two sections: based with 11 bits and the extended id with 18 bits. b.1. based id the based id consists of 11 bits. it is transmi tted in the order from id-28 to id-18. it is equivalent to format of the standard identif ier. the based id defines the extended frame?s base priority. b.2. extended id the extended id consists of 18 bits. it is tr ansmitted in the order of id-17 to id-0. in a standard format, the identifier is followed by rtr bit. rtr bit : remote transmission request bit (standard format as well as extended format) in data frames, the rtr bit has to be ?dom inant?. within a remote frame the rtr bit numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 424 - revision v1.06 has to be ?recessive?. in an extended format the ba se id is transmitted first, followed by the ide bit and the srr bit. the extended id is transmitted after the srr bit. srr bit : substitute remote request bit (extended format) the srr is recessive bit. it is transmitted in ext ended format at the position of the rtr bit in standard frames and so substitutes the rtr-bit in the standard format. ide bit : identifier extension bit (extended format) the ide bit belongs to (a). the arbitration field for the extended format. (b). the control field for the standard format. 4 control field : (standard format as well as extended format) the control filed consists of six bits. the format of the control field is different for standard format and extended format. frames in standard format include the data length code, the ide bit, which is transmitted ?dominant?, and the reserved bit r0. frames in the extended format include the data le ngth code and two reserved bit r1 and r0. the reserved bits have to be sent ?dominant?, but receivers accept ?dominant? and ?recessive? bits in all combinations. figure 5-78 format of control field data length code : (standard format as well as extended format) the number of bytes in the data field is in dicated by the data length code. the data length code is 4 bits width and is transmi tted within the control field. the acceptable number of data length is from 0 to 8 bytes. 5 data field (standard format as well as extended format) the data field consists of the data to be tran sferred within a data frame. it can contain from 0 to 8 bytes, and each byte contains 8 bits which are transferred from msb first. 6 crc field (standard format as well as extended format) contains the crc sequence followed by a crc delimiter numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 425 - revision v1.06 figure 5-79 format of crc field crc sequence (standard format as well as extended format) the frame check sequence is derived from a cyclic redundancy code best suited for frame with bit counts less than 127 bits (bch code). in order to carry out the crc calculation, the polynomial to be divided is defined as the polynomial, the coefficients of which are given by the de-stuffed bit stream consisting of start of frame, arbitration field, control field, data filed (if present) and for the 15 lowest coefficients, by 0. this polynom ial is divided by the generator-polynomial: x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 the remainder of this polynomial division is the crc sequence transmitted over the bus. crc delimiter (standard format as well as extended format) the crc sequence is followed by the crc delimiter which cons ists of a single ?recessive? bit. 7 ack field (standard format as well as extended format) the ack filed is two bits long and contains the ack slot and the ack delimiter. in the ack filed, the transmitting station sends two ?recessive? bits. a receiver which has received a valid message correctly, reports this to the transmitter by sending a ?dominant? bi t during the ack slot (it sends ?ack?). numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 426 - revision v1.06 figure 5-80 format of ack field ack slot: all stations having received the matching crc_ sequence report this within the ack slot by super-scribing the ?recessive? bit of the transmitter by a ?dominant? bit ack delimiter: the ack delimiter is the second bit of the ack filed and has to be a ?recessive? bit. as a consequence, the ack slot is surrounded by two ?recessive? bits (crc delimiter, ack delimiter). 8 end of frame (standard format as well as extended format) each data frame and remote frame is del imited by a flag sequence consisting of seven ?recessive? bits. 5.13.4.4 remote frame a station acting as a receiver for certain data can initiate the transmission of the respective data by its source node by sending a remote fr ame. there are also two kinds of formats, standard format and extended format, are exist ed in the remote frame. in both these formats, it composed of six different bit fi elds: start of frame, arbitration field, control filed, crc filed, ack field and end of frame. contrary to data frames, the rtr bit of remo te frame is ?recessive?. there is no data filed, independent of the values of the data length code which may be signed any value within the admissible range 0?8. the value is the data length code of the corresponding data frame. the polarity of the rtr bit indicated whether a transmitted frame is a data frame (rtr bit ?dominant?) or a remote frame (rtr bit ?recessive?). numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 427 - revision v1.06 figure 5-81 format of remote frame 5.13.4.5 error frame the erro r frame consists of two different fields . the first field is given by the super-position of error flag contributed from different stations. the following second field is the error delimiter. figure 5-82 format of error frame there are 2 forms of error flag: an active error flag and a passive error flag. the active error flag consists of six cons ecutive ?dominant? bits. the passive error flag consists of six consecutive ?recessive? bits unless it is overwritten by ?dominant? bits from other nodes. the error delimiter consists of eight ?reces sive? bits. after tran smission of an error flag, each station sends ?recessive? bits and monito rs the bus until it detects a ?recessive? bit. afterwards it starts transmitti ng seven more ?recessive? bits. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 428 - revision v1.06 5.13.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value can0_ba = 0x4018_0000 mode can0_ba+0x00 r/w mode register 0x0000_0000 command can0_ba+0x04 r/w command register 0x0000_0000 bussts can0_ba+0x08 r bus status register 0x0000_0140 intr can0_ba+0x0c r/w interrupt status register 0x0000_0000 inten can0_ba+0x10 r/w interrupt enable register 0x0000_0000 btimr can0_ba+0x14 r/w bit timing register 0x0000_1100 errcr can0_ba+0x20 r error capture register 0x0000_0000 recntr can0_ba+0x28 r receiver error counter register 0x0000_0000 tecntr can0_ba+0x2c r/w transmit error counter register 0x0000_0000 txfinfo can0_ba+0x30 r/w transmit frame information register 0x0000_0000 txidr can0_ba+0x34 r/w transmit identifier register 0x0000_0000 txdata_a can0_ba+0x38 r/w transmit data register a 0x0000_0000 txdata_b can0_ba+0x3c r/w transmit data register b 0x0000_0000 rxfinfo can0_ba+0x40 r received frame information register 0x0000_0000 rxidr can0_ba+0x44 r received identifier register 0x0000_0000 rxdata_a can0_ba+0x48 r received data register a 0x0000_0000 rxdata_b can0_ba+0x4c r received data register b 0x0000_0000 acr can0_ba+0x50 r/w acceptance code register 0x0000_0000 amr can0_ba+0x54 r/w acceptance mask register 0xffff_ffff numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 429 - revision v1.06 5.13.6 register description mode register (mode) register offset r/w description reset value mode can0_ba+0x00 r/w can bus operation mode register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved lom rstm bits descriptions [31:2] reserved reserved [1] lom listen only mode if this bit is enabled, it can receive the input data but doesn?t response the ack signal if the receiver id that matches the default value. 1 = enable the listen only mode. 0 = absent [0] rstm reset mode it is used to disable the re transmission function and reset the h/w state machine into the idle state. 1 = reset mode 0 = absent numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 430 - revision v1.06 command register (command) register offset r/w description reset value command can0_ba+0x04 r/w command register 0x0000_0100 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved hw_sync 7 6 5 4 3 2 1 0 can_en wakeup_en reserved abrt txreq bits descriptions [31:9] reserved reserved [8] hw_sync hardware synchronization it is used to define the time quantum offset is calculated by hardware or configured by the parameter of sjw which defined in the btimr register. 1 = enable the hardware synchronization. the bit timing synchronization is done by ha rdware and the time quantum offset is calculated automatically by internal hardware design. 0 = disable the hardware synchronization. the time quantum offset for the bit ti ming synchronization is configured in the parameter of sjw which defined in btimr register. note: the time quantum offset is used to compensate the propagation delay or phased shifts of can bus line. [7] can_en can controller enable 1 = enable the can controller 0 = disable the can controller [6] wakeup_en wake up enable 1 = enable the wake up function it will enable the wake up function when the system is in sleep mode. as the received signal (rx) toggle from ?r ecessive? to ?dominant? on the can bus and the wakeup_en bit is set to 1, it will wake up the system. 0 = disable the wake up function note: when the system had been wake up, this bit must be clear before the user clears the interrupt flag wui. [5:2] reserved reserved [1] abrt abort automatic re-transmission 1 = abort automatic re-transmission after a message transmission failure numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 431 - revision v1.06 0 = automatic re-transmission wh en a message transmission failure [0] txreq transmission request 1 = a message shall be transmitted out 0 = absent numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 432 - revision v1.06 bus status register (bussts) register offset r/w description reset value bussts can0_ba+0x08 r bus status register 0x0000_0140 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved epassive eactive 7 6 5 4 3 2 1 0 busoff busidle txsts rxsts txcomplet reserved bits descriptions [31:10] reserved reserved [9] epassive error passive status 1 = the bus stays in error passive state 0 = the bus doesn?t stay in error passive state [8] eactive error active status 1 = the bus stays in error active state 0 = the bus doesn?t stay in error active state [7] busoff bus on/off status 1 = bus is in off state 0 = bus is in on status; it can be in active or passive state [6] busidle bus idle status 1 = bus is in idle; the controller is not involved in bus activities 0 = there is bus transmit or bus toggle in received bus signal [5] txsts transmit status 1 = transmitting; the bus is transmitting a message 0 = idle [4] rxsts receive status 1 = receiving; the controller is receiving a message 0 = idle [3] txcomplet transmission complete status 1 = the current requested transmission has been completed successfully 0 = incomplete numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 433 - revision v1.06 [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 434 - revision v1.06 interrupt status register (intr) register offset r/w description reset value intr can0_ba+0x0c r/w interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 bei ali reserved wui reserved ti ri bits descriptions [31:8] reserved reserved [7] bei bus error interrupt 1 = this bit will be set when this can node detects an error on the can-bus and the beie bit is set within the interrupt enable register. it will be clear by write 1 to this bit. 0 = no bus error interrupt [6] ali arbitration lost interrupt 1 = this bit will be set when this can node lose the arbitration to become a receiver and the alie bit is set within the interrupt enable register. it will be clear by write 1 to this bit. 0 = no arbitration lost interrupt [5] reserved reserved [4] wui wake-up interrupt 1 = this bit will be set when this can node is sleeping but be waked up by bus activity and the wuie bit is set within the interrupt enable register. it will be clear by write 1 to this bit. if the wakeup interrupt active after power idle, the wakeup_en bit shall be clear before this bit to be cleared. 0 = no wake-up interrupt [3:2] reserved reserved [1] ti transmit interrupt 1 = this bit will be set when a transmission has done and the tie bit is set within the interrupt enable register. it will be clear by write 1 to this bit. 0 = no transmit done information [0] ri receive interrupt 1 = this bit will be set when a frame receiving has done and the rie bit is set within the interrupt register. it will be clear by write 1 to this bit. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 435 - revision v1.06 0 = no more received message within the rxfifo numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 436 - revision v1.06 interrupt enable register (inten) register offset r/w description reset value inten can0_ba+0x10 r/w interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 beie alie reserved wuie reserved tie rie bits descriptions [31:8] reserved reserved [7] beie bus error interrupt enable 1 = enable bus error interrupt 0 = disable [6] alie arbitration lost interrupt enable 1 = enable arbitration lost interrupt 0 = disable [5] reserved reserved [4] wuie wake-up interrupt enable 1 = enable wake-up interrupt 0 = disable [3:2] reserved reserved [1] tie transmit interrupt enable 1 = enable transmit done interrupt 0 = disable [0] rie receive interrupt enable 1 = enable receive done interrupt 0 = disable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 437 - revision v1.06 bus timing register (btimr) register offset r/w description reset value btimr can0_ba+0x14 r/w bus timing register 0x0000_1100 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 samp tseg2 tseg1[4:2] 7 6 5 4 3 2 1 0 tseg1[1:0] sjw reserved bits descriptions [31:16] reserved reserved [15] samp number of sampling point 1 = triple; the bus is sampled three times in one bit; they are located in tseg1 + 1, tseg1 and tseg1 - 1. recommended for low/medium speed buses wher e filtering spikes on the bus line is beneficial 0 = single; the bus is sampled once in the location of (tseg1 + 1); recommended for high speed buses. [14:11] tseg2 time segment 2 (tseg1 + 1) and (tseg2 + 1) define the number of clock cycles per bit period and the location of the sample point. (tseg2 +1) defines the sample point location of per bit before the sync seg. note: there are three segments including sync, tseg1, and tseg2 per bit. the value of tseg2 is max (tseg1/2, 2). [10:6] tseg1 time segment 1 (tseg1 + 1) defines the period between the sync segment and the sample point (not including the sync segment). the maximum value of tseg1 is 16 and the minimum value is 2. [5:4] sjw synchronization jump width to compensate for phase shifts between clo ck sources of different bus nodes, any node must re-synchronize on any relevant si gnal edge of the current transmission. the sjw defines the maximum number of clock cycles a bit period may be shorted or lengthened by one re-synchronization. the maxi mum values of sjw shall be less than the min{tseg1, tseg2}. (see the btimr block description) [3:0] reserved reserved note: according the parameters which defined in the btimr, the bit rate clock of can can be calculated as following equation. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 438 - revision v1.06 )321)(1 ( ++ + = tseg tseg divider fout canbps where: canbps: can bit rate fout: can clock source divider: can clock divide number (refer to clock control register) tseg1: time segment 1 tseg2: time segment 2 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 439 - revision v1.06 error capture register (errcr) register offset r/w description reset value errcr can0_ba+0x20 r error capture register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved id18_nm id11_nm stuff_err s form_errs crc_errs ack_errs bit_errs bits descriptions [31:7] reserved reserved [6] id18_nm id18 not match status 1 = 18-bit identify pattern doesn?t match t he received data. the status will be updated when there is crc error or be cleared by write ?0?. 0 = 18-bit identify pattern matches the received data. [5] id11_nm id11 not match status 1 = 11-bit identify pattern doesn?t match t he received data. the status will be updated when there is crc error or be cleared by write ?0?. 0 = 11-bit identify pattern matches the received data. [4] stuff_errs stuff error 1 = a stuff error has to be detected at the bi t time of the 6th consecutive equal bit level in a message field that should be c oded by the method of bit stuffing. 0 = no stuff error. [3] form_errs form error 1 = a form error has to be detected when a fi xed-form bit field contains one or more illegal bits. the fixed-form includes the crc delimiter, ack delimiter, error message delimiter, overflow delimiter and eof. 0 = no fixed form error. [2] crc_errs crc error 1 = the crc sequence consists of the result of the crc calculation by the transmitter. the receiver calculates the crc in the same way as the transmitter. a crc error has to be detected, if the calculated result is not the same as the received in the crc sequence. 0 = no crc error. [1] ack_errs acknowledge error 1 = an acknowledge error has to be detect ed by a transmitter whenever it does not numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 440 - revision v1.06 monitor a ?dominant? bit during the ack slot. 0 = no acknowledge error [0] bit_errs bit error 1 = a node that is sending a bit on the bus also monitors the bus. a bit error has to be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. 0 = no bit error numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 441 - revision v1.06 rx error count register (recntr) register offset r/w description reset value recntr can0_ba+0x28 r receiver error counter register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 recnt[7:0] bits descriptions [31:8] reserved reserved [7:0] recnt receiver error counter the rx error counter register reflects the current value of the receive error counter. in operating mode, this register appears to the cpu as a read only memory. (if a bus-off event occurs, the recnt is initialized to 0) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 442 - revision v1.06 tx error count register (tecntr) register offset r/w description reset value tecntr can0_ba+0x2c r transmit error counter register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 tecnt[7:0] bits descriptions [31:8] reserved reserved [7:0] tecnt transmit error counter the tx error counter register reflects the cu rrent value of the transmit error counter. in operating mode, this register appears to the cpu as a read only memory. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 443 - revision v1.06 tx frame information register (txfinfo) register offset r/w description reset value txfinfo can0_ba+0x30 r/w tx frame information register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 txff txrtr txdlc[5:0] bits descriptions [31:8] reserved reserved [7] txff transmit frame format 1 = the format of transmission frame is extended format 0 = the format of transmission frame is standard format [6] txrtr remote transmission request 1 = the transmission frame is remote frame (standard format as well as extended format) 0 = the transmission frame is data frame [5:0] txdlc transmit data length code the number of bytes in the data field is indicated by the txdlc. number of data bytes dlc[3] dlc[2] dlc[1] dlc[0] 0 1 2 3 4 5 6 7 8 d d d d d d d d r d d d d r r r r d d d r r d d r r d d r d r d r d r d note: where ?d? means dominant bit, 0, and ?r? means recessive bit, 1. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 444 - revision v1.06 tx identifier register (txidr) register offset r/w description reset value txidr can0_ba+0x34 r/w transmit identifier register 0x0000_0000 31 30 29 28 27 26 25 24 txid[28:21] 23 22 21 20 19 18 17 16 txid[20:13] 15 14 13 12 11 10 9 8 txid[12:5] 7 6 5 4 3 2 1 0 txid[4:0] reserved bits descriptions [31:3] txid transmit identifier txid[28:18] is the 11-bit identifier for standard format txid[28:0] is the 29-bit identifier for extended format [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 445 - revision v1.06 tx data_a register (txdata_a) register offset r/w description reset value txdata_a can0_ba+0x38 r/w transmit data register a 0x0000_0000 31 30 29 28 27 26 25 24 txdata4 23 22 21 20 19 18 17 16 txdata3 15 14 13 12 11 10 9 8 txdata2 7 6 5 4 3 2 1 0 txdata1 bits descriptions [31:24] txdata4 transmit data buffer 4 txdata4 is the 4th transmit data buffer. if the txdlc >= 6?h4, the content of this buffer is the 4th data will be sent out during data field [23:16] txdata3 transmit data buffer 3 txdata3 is the 3rd transmit data buffer. if the txdlc >= 6?h3, the content of this buffer is the 3rd data will be sent out during data field [15:8] txdata2 transmit data buffer 2 txdata2 is the 2nd transmit data buffer. if the txdlc >= 6?h2, the content of this buffer is the 2nd data will be sent out during data field [7:0] txdata1 transmit data buffer 1 txdata1 is the 1st transmit data buffer. if the txdlc >= 6?h1, the content of this buffer is the 1st data will be sent out during data field numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 446 - revision v1.06 tx data_b register (txdata_b) register offset r/w description reset value txdata_b can0_ba+0x3c r/w transmit data register b 0x0000_0000 31 30 29 28 27 26 25 24 txdata8 23 22 21 20 19 18 17 16 txdata7 15 14 13 12 11 10 9 8 txdata6 7 6 5 4 3 2 1 0 txdata5 bits descriptions [31:24] txdata8 transmit data buffer 8 txdata8 is the 8th transmit data buffer. if t he txdlc = 6?h8, the content of this buffer is the 8th data will be sent out during data field [23:16] txdata7 transmit data buffer 7 txdata7 is the 7th transmit data buffer. if the txdlc >= 6?h7, the content of this buffer is the 7th data will be sent out during data field [15:8] txdata6 transmit data buffer 6 txdata6 is the 6th transmit data buffer. if the txdlc >= 6?h6, the content of this buffer is the 6th data will be sent out during data field [7:0] txdata5 transmit data buffer 5 txdata5 is the 5th transmit data buffer. if the txdlc >= 6?h5, the content of this buffer is the 5th data will be sent out during data field numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 447 - revision v1.06 rx frame information register (rxfinfo) register offset r/w description reset value rxfinfo can0_ba+0x40 r rx frame information register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rxide rxrtr reserved rxdlc[3:0] bits descriptions [31:8] reserved reserved [7] rxide receiver identifier extended bit 1 = the format of received frame is extended format 0 = the format of received frame is standard format [6] rxrtr receive remote transmission request bit 1 = the received frame is remote frame 0 = the received frame is data frame [5:4] reserved reserved [3:0] rtxdlc receive data length code the number of bytes in the data field is indicated by the rxdlc. number of data bytes dlc[3] dlc[2] dlc[1] dlc[0] 0 1 2 3 4 5 6 7 8 d d d d d d d d r d d d d r r r r d d d r r d d r r d d r d r d r d r d note: where ?d? means dominant bit, 0, and ?r? means recessive bit, 1. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 448 - revision v1.06 received identifier register (rxidr) register offset r/w description reset value rxidr can0_ba+0x44 r received identifier register 0x0000_0000 31 30 29 28 27 26 25 24 rxid[28:21] 23 22 21 20 19 18 17 16 rxid[20:13] 15 14 13 12 11 10 9 8 rxid[12:5] 7 6 5 4 3 2 1 0 rxid[4:0] reserved bits descriptions [31:3] rxid receive identifier rxid[28:18] is the 11-bit identifier for standard format rxid[28:0] is the29-bit identifier for extended format [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 449 - revision v1.06 rx data_a register (rxdata_a) register offset r/w description reset value rxdata_a can0_ba+0x48 r receive data register a 0x0000_0000 31 30 29 28 27 26 25 24 rxdata4 23 22 21 20 19 18 17 16 rxdata3 15 14 13 12 11 10 9 8 rxdata2 7 6 5 4 3 2 1 0 rxdata1 bits descriptions [31:24] rxdata4 receive data buffer 4 rxdata4 is the 4th receive data buffer. if the rxdlc >= 4?h4, the content of this buffer will be filled with the 4th data during data field [23:16] rxdata3 receive data buffer 3 rxdata3 is the 3rd receive data buffer. if the rxdlc >= 4?h3, the content of this buffer will filled with the 3rd data during data field [15:8] rxdata2 receive data buffer 2 rxdata2 is the 2nd receive data buffer. if the rxdlc >= 4?h2, the content of this buffer will be filled with the 2nd data during data field [7:0] rxdata1 receive data buffer 1 rxdata1 is the 1st receive data buffer. if the rxdlc >= 4?h1, the content of this buffer will be filled with the 1st data during data field numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 450 - revision v1.06 rx data_b register (rxdata_b) register offset r/w description reset value rxdata_b can0_ba+0x4c r receive data register b 0x0000_0000 31 30 29 28 27 26 25 24 rxdata8 23 22 21 20 19 18 17 16 rxdata7 15 14 13 12 11 10 9 8 rxdata6 7 6 5 4 3 2 1 0 rxdata5 bits descriptions [31:24] rxdata8 receive data buffer 8 rxdata8 is the 8th receive data buffer. if the rxdlc = 4?h8, the content of this buffer will be filled with the 8th data during data field [23:16] rxdata7 receive data buffer 7 rxdata7 is the 7th receive data buffer. if the rxdlc >= 4?h7, the content of this buffer will be filled with the 7th data during data field [15:8] rxdata6 receive data buffer 6 rxdata6 is the 6th receive data buffer. if the rxdlc >= 4?h6, the content of this buffer will be filled with the 6th data during data field [7:0] rxdata5 receive data buffer 5 rxdata5 is the 5th receive data buffer. if the rxdlc >= 4?h5, the content of this buffer will be filled with the 5th data during data field numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 451 - revision v1.06 acceptance code register (acr) register offset r/w description reset value acr can0_ba+0x50 r/w acceptance code register 0x0000_0000 31 30 29 28 27 26 25 24 acrid[28:21] 23 22 21 20 19 18 17 16 acrid[20:13] 15 14 13 12 11 10 9 8 acrid[12:5] 7 6 5 4 3 2 1 0 acrid[4:0] reserved bits descriptions [31:3] acrid acceptance code register the bit patterns (identifier) of received message are defined within the acceptance code registers. acrid[28:18] is used to identify the received message of 11-bit identify. acrid[28:0] is used to identify the received message of 29-bit identify. [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 452 - revision v1.06 acceptance mask register (amr) register offset r/w description reset value amr can0_ba+0x54 r/w acceptance mask register 0xffff_ffff 31 30 29 28 27 26 25 24 amrid[28:21] 23 22 21 20 19 18 17 16 amrid[20:13] 15 14 13 12 11 10 9 8 amrid[12:5] 7 6 5 4 3 2 1 0 amrid[4:0] reserved bits descriptions [31:3] amrid acceptance mask register the corresponding acceptance mask register s allow defining certain bit position to be mask or to be ?don?t care?. 1 = the corresponding bit is masked and it depends on the acr bit and its received data bit. 0 = the corresponding bit is always pass. amrid[28:18] is used to identify the received message of 11-bit identify. amrid[28:0] is used to identify the received message of 29-bit identify. [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 453 - revision v1.06 5.14 ps2 device controller (ps2d) 5.14.1 overview ps/2 device controller provides basic timing control for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the re ceived/transmit code needs to be translated as meaningful code by firmware. the device controll er generates the clk signal after receiving a request to send, but host has ultimate control ov er communication. data sent from the host to the device is read on the rising edge and data sent from device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s/w can select 1 to 16 bytes for a continuous transmission. 5.14.2 features z host communication inhibit and request to send detection z reception frame error detection z programmable 1 to 16 bytes transmit buffer to reduce cpu intervention z double buffer for data reception z s/w override bus numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 454 - revision v1.06 5.14.3 block diagram the ps/2 device controller consists of apb inte rface and timing control logic for data and clk lines. apb bus figure 5-83 ps/2 device block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 455 - revision v1.06 5.14.4 functional description 5.14.4.1 communication the ps/2 device impleme nts a bidirectional synchro nous serial protocol. the bus is "idle" when both lines are high (open-collector). this is the only state where the device is allowed start to transmit data. the host has ultimate control over the bus and may inhibit communication at any time by pulling the clk line low. the clk signal is generated by ps2 device. if the host wants to send data, it must first inhibit communication from the device by pulling clk low. the host then pulls data low and releases clk. this is the "request-to-send" state and si gnals the device to start generating clk pulses. data clk bus state high high idle high low communication inhibit low high host request to send all data is transmitted one byte at a time and each by te is sent in a frame consisting of 11 or 12 bits. these bits are: z 1 start bit. this is always 0 z 8 data bits, least significant bit first z 1 parity bit (odd parity) z 1 stop bit. this is always 1 z 1 acknowledge bit (host-to-device communication only) the parity bit is set if there is an even number of 1's in the data bits and cleared to 0 if there is an odd number of 1's in the data bits. the number of 1's in the data bits plus the parity bit always add up to an odd number set to 1. this is used for error detection. the device must check this bit and if incorrect it should respond as if it had received an invalid command. the host may inhibit communication at any time by pulling the clk line low for at least 100 microseconds. if a transmission is inhibited befor e the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current data when host releases clock. in order to reserve enough time for s/w to decode ho st command, the transmit logic is blocked by rxint bit, s/w must clear rxint bit to start re transmit. s/w can write clrfifo to 1 to reset fifo pointer if need. device-to-host the device uses a serial protocol with 11-bit frames. these bits are: z 1 start bit. this is always 0 z 8 data bits, least significant bit first z 1 parity bit (odd parity) z 1 stop bit. this is always 1 the device writes a bit on the data line when clk is high, and it is read by the host when clk is low. figure 5-84 in the following illustrate this. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 456 - revision v1.06 clk data start data0 data1 data2 data3 data4 data5 data6 data7 stop parity device t o host figure 5-84 data format of device-to-host host-to-device: first of all, the ps/2 device always generates the clk signal. if the host wants to send data, it must first put the clk and data lines in a "request-to-send" state as follows: z inhibit communication by pulling clk low for at least 100 microseconds z apply "request-to-send" by pulling data low, then release clk the device should check for this state at interv als not to exceed 10 milliseconds. when the device detects this state, it will begin generating clk signals and clk in eight data bits and one stop bit. the host changes the data line only when the clk line is low, and data is read by the device when clk is high. after the stop bit is received, the device will acknowledge the received byte by bringing the data line low and generating one last clk pulse. if the host does not release the data line after the 11th clk pulse, the device will continue to generat e clk pulses until the data line is released. start data0 data1 data2 data3 data4 data5 data6 data7 parity stop ack clk data host to device figure 5-85 data format of host-to-device numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 457 - revision v1.06 the host and the device data and clk detailed timing for communication is shown as below: figure 5-86 ps/2 bit data format 5.14.4.2 ps/2 bus timing specification clk data t1 t2 t4 t3 1st clk 10th clk 2nd clk 11th clk start bit bit0 parity bit stop bit t5 data t9 t8 t7 i/o inhibit start bit bit0 parity bit stop bit 10th clk 9th clk 11th clk 2nd clk 1st clk ss ss ss ss ss ss clk ps2 device data output ps2 device data input figure 5-87 ps/2 bus timing numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 458 - revision v1.06 symbol timing parameter min max t1 data transition to the falling edge of clk 5us 25us t2 rising edge of clk to data transition 5us t4-5us t3 duration of clk inactive 30us 50us t4 duration of clk active 30us 50us t5 time to auxiliary device inhibit after clock 11 to ensure auxiliary device does not start another transmission >0 50us t7 duration of clk inactive 30us 50us t8 duration of clk active 30us 50us t9 time from inactive to active clk transition, use to time auxiliary device sample data 5us 25us numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 459 - revision v1.06 5.14.4.3 tx fifo operation writing ps2t xdata0 register starts device to host communication. s/w is required to define txfifo depth before writing transmission data to tx fifo. 1st start bit is sent to ps2 bus 100us after s/w writes tx fifo, if there is mo re than 4 bytes data need to be sent, s/w can write residual data to ps2txdata1-3 before 4th byte transmit complete. a time delay 100us is added between two consecutive bytes. figure 5-88 ps/2 data format numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 460 - revision v1.06 5.14.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value ps2_ba: 0x4010_0000 ps2con ps2_ba+0x00 r/w ps2 control register 0x0000_0000 ps2txdata0 ps2_ba+0x04 r/w ps2 transmit data register 0 0x0000_0000 ps2txdata1 ps2_ba+0x08 r/w ps2 transmit data register 1 0x0000_0000 ps2txdata2 ps2_ba+0x0c r/w ps2 transmit data register 2 0x0000_0000 ps2txdata3 ps2_ba+0x10 r/w ps2 transmit data register 3 0x0000_0000 ps2rxdata ps2_ba+0x14 r ps2 receive data register 0x0000_0000 ps2status ps2_ba+0x18 r/w ps2 status register 0x0000_0083 ps2intid ps2_ba+0x1c r/w ps2 interrupt identification register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 461 - revision v1.06 5.14.6 register description ps2 control register (ps2con) register offset r/w description reset value ps2con ps2_ba + 0x00 r/w ps2 control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved fps2dat fps2clk override clrfifo 7 6 5 4 3 2 1 0 ack txfifo_depth rxinten txinten ps2en bits descriptions [31:12] reserved reserved [11] fps2dat force ps2data line it forces ps2data high or low regardless of the internal state of the device controller if override is set to high. 1 = force ps2data high 0 = force ps2data low [10] fps2clk force ps2clk line it forces ps2clk line high or low regardle ss of the internal state of the device controller if override is set to high. 1 = force ps2data line high 0 = force ps2data line low [9] override software override ps2 clk/data pin state 1 = ps2clk and ps2data pins are controlled by s/w 0 = ps2clk and ps2data pins are controlled by internal state machine. [8] clrfifo clear tx fifo write 1 to this bit to terminate device to host transmission. the txempty bit in ps2status bit will be set to 1 and pointer by teidex is reset to 0 regardless there is residue data in buffer or not. the buffer content is not been cleared. 1 = clear fifo 0 = not active [7] ack acknowledge enable 1 = if parity error or stop bit is not received correctly, acknowledge bit will not be sent to numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 462 - revision v1.06 host at 12th clock 0 = always send acknowledge to host at 12t h clock for host to device communication. [6:3] txfifodipth transmit data fifo depth there is 16 bytes buffer for data transmit. s/w can define the fifo depth from 1 to 16 bytes depends on application. 0 = 1 byte 1 = 2 bytes ? 14 = 15 bytes 15 = 16 bytes [2] rxinten enable receive interrupt 1 = enable data receive complete interrupt 0 = disable data receive complete interrupt [1] txinten enable transmit interrupt 1 = enable data transmit complete interrupt 0 = disable data transmit complete interrupt [0] ps2en enable ps2 device enable ps2 device controller 1 = enable 0 = disable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 463 - revision v1.06 ps2 tx data register 0-3 (ps2txdata0-3) register offset r/w description reset value ps2txdata0 ps2_ba + 0x04 r/w ps2 transmit data register0 0x0000_0000 ps2txdata1 ps2_ba + 0x08 r/w ps2 transmit data register1 0x0000_0000 ps2txdata2 ps2_ba + 0x0c r/w ps2 transmit data register2 0x0000_0000 ps2txdata3 ps2_ba + 0x10 r/w ps2 transmit data register3 0x0000_0000 31 30 29 28 27 26 25 24 ps2txdatax[31:24] 23 22 21 20 19 18 17 16 ps2txdatax[23:16] 15 14 13 12 11 10 9 8 ps2txdatax[15:8] 7 6 5 4 3 2 1 0 ps2txdatax[7:0] bits descriptions [31:0] ps2txdatax transmit data write data to this register starts device to host communication if bus is in idle state. s/w must enable ps2en before writing data to tx buffer. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 464 - revision v1.06 ps2 receiver data register (ps2rxdata ) register offset r/w description reset value ps2rxdata ps2_ba + 0x14 r/w ps2 receive data register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rxdata[7:0] bits descriptions [31:8] reserved reserved [7:0] ps2rxdata received data for host to device communication, after a cknowledge bit is sent, the received data is copied from receive shift register to ps2rxda ta register. cpu must read this register before next byte reception complete, other wise the data will be overwritten and rxovf bit in ps2status[6] will be set to 1. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 465 - revision v1.06 ps2 status register (ps2status) register offset r/w description reset value ps2status ps2_ba + 0x18 r/w ps2 status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved byteidx[3:0] 7 6 5 4 3 2 1 0 txempty rxovf txbusy rxbusy rxparity framerr ps2data ps2clk bits descriptions [31:12] reserved reserved [11:8] byteidx byte index it indicates which data byte in transmit data shift register. when all data in fifo is transmitted and it will be cleared to 0. it is a read only bit. byteidx data transmit byteidx data transmit 0000 txdata0[7:0] 1000 txdata2[7:0] 0001 txdata0[15:8] 1001 txdata2[15:8] 0010 txdata0[23:16] 1010 txdata2[23:16] 0011 txdata0[31:24] 1011 txdata2[31:24] 0100 txdata1[7:0] 1100 txdata3[7:0] 0101 txdata1[15:8] 1101 txdata3[15:8] 0110 txdata1[23:16] 1110 txdata3[23:16] 0111 txdata1[31:24] 1111 txdata3[31:24] [7] txempty tx fifo empty when s/w writes any data to ps2txdata0-3 the txempty bit is cleared to 0 immediately if ps2en is enabled. when tr ansmitted data byte number is equal to fifodepth then txempty bit is set to 1. 1 = fifo is empty 0 = there is data to be transmitted read only bit. [6] rxovf rx buffer overwrite 1 = data in ps2rxdata register is overwritten by new received data numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 466 - revision v1.06 0 = no overwrite write 1 to clear this bit. [5] txbusy transmit busy this bit indicates that the ps2 device is currently sending data. 1 = currently sending data 0 = idle read only bit. [4] rxbusy receive busy this bit indicates that the ps2 dev ice is currently receiving data. 1 = currently receiving data 0 = idle read only bit. [3] rxparity received parity this bit reflects the parity bit for t he last received data byte (odd parity). read only bit. [2] framerr frame error for host to device communication, if stop bi t (logic 1) is not re ceived it is a frame error. if frame error occurs, data line may keep at low state after 12th clock. at this moment, s/w overrides ps2clk to send clock till ps2data release to high state. after that, device sends a ?resend? command to host. 1 = frame error occur 0 = no frame error write 1 to clear this bit. [1] ps2data data pin state this bit reflects the status of the ps2 data line after synchronizing and sampling. [0] ps2clk clk pin state this bit reflects the status of the ps2clk line after synchronizing. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 467 - revision v1.06 ps2 interrupt identification register (ps2intid) register offset r/w description reset value ps2intid ps2_ba + 0x1c r/w ps2 interrupt identification register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved txint rxint bits descriptions [31:3] reserved reserved [1] txint transmit interrupt this bit is set to 1 after stop bit is transmitt ed. interrupt occur if txinten bit is set to 1. 1 = transmit interrupt occurs 0 = no interrupt write 1 to clear this bit to 0. [0] rxint receive interrupt this bit is set to 1 when acknowledge bit is sent for host to device communication. interrupt occurs if rxinten bit is set to 1. 1 = receive interrupt occurs 0 = no interrupt write 1 to clear this bit to 0. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 468 - revision v1.06 5.15 i 2 s controller (i 2 s) 5.15.1 overview the i 2 s controller consists of iis protocol to inte rface with external audio codec. two 8 word deep fifo for read path and write path respectively and is capable of handling 8 ~ 32 bit word sizes. dma controller handles the data movement between fifo and memory. 5.15.2 features z i 2 s can operate as either master or slave z capable of handling 8, 16, 24 and 32 bit word sizes z mono and stereo audio data supported z i 2 s and msb justified data format supported z two 8 word fifo data buffers are provided, one for transmit and one for receive z generates interrupt requests when buffer levels cross a programmable boundary z two dma requests, one for transmit and one for receive numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 469 - revision v1.06 5.15.3 block diagram figure 5-89 i 2 s clock control diagram figure 5-90 i 2 s controller block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 470 - revision v1.06 5.15.4 functional description 5.15.4.1 i 2 s operation msb lsb msb word n-1 right channel word n left channel word n+1 right channel i2sbclk i2slrclk i2sdi / i2sdo figure 5-91 i 2 s bus timing diagram (format =0) msb lsb msb word n-1 right channel word n lef channel word n+1 right channel i2sbclk i2slrclk i2sdi / i2sdo figure 5-92 msb justified timing diagram (format=1) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 471 - revision v1.06 5.15.4.2 fifo operation n+2 n+1 n n+3 77770 0 0 0 right+1 left right left+1 77770 0 0 0 n n+1 right left 0 15 0 15 0 15 0 15 mono 8-bit data mode stereo 8-bit data mode mono 16-bit data mode stereo 16-bit data mode n left right n n+1 0 0 0 mono 24-bit data mode stereo 24-bit data mode 23 23 23 n left right n n+1 0 31 31 31 0 0 mono 32-bit data mode stereo 32-bit data mode figure 5-93 fifo contents for various i 2 s modes numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 472 - revision v1.06 5.15.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value i2s_ba = 0x401a_0000 i2s_con i2s_ba+0x00 r/w i 2 s control register 0x0000_0000 i2s_clkdiv i2s_ba+0x04 r/w i 2 s clock divider register 0x0000_0000 i2s_ie i2s_ba+0x08 r/w i 2 s interrupt enable register 0x0000_0000 i2s_status i2s_ba+0x0c r/w i 2 s status register 0x0014_1000 i2s_txfifo i2s_ba+0x10 r/w i 2 s transmit fifo register 0x0000_0000 i2s_rxfifo i2s_ba+0x14 r/w i 2 s receive fifo register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 473 - revision v1.06 5.15.6 register description i 2 s control register (i2s_con) register offset r/w description reset value i2s_con i2s_ba+0x00 r/w i 2 s control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved reserved rxdma txdma clr_rxfifo clr_txfifo lchzcen rchzcen 15 14 13 12 11 10 9 8 mclken rxth[2:0] txth[2:0] slave 7 6 5 4 3 2 1 0 format mono wordwidth mute rxen txen i2sen bits descriptions [31:22] reserved reserved [21] rxdma enable receive dma when rx dma is enabled, i 2 s requests dma to transfer data from receive fifo to sram if fifo is not empty. 1 = enable rx dma 0 = disable rx dma [20] txdma enable transmit dma when tx dma is enables, i 2 s request dma to transfer data from sram to transmit fifo if fifo is not full. 1 = enable tx dma 0 = disable tx dma [19] clr_rxfifo clear receive fifo write 1 to clear receive fifo, internal pointer is reset to fifo start point, and rxfifo_level[3:0] returns to zero and receive fifo becomes empty. this bit is cleared by hardware automatically, read it return zero. [18] clr_txfifo clear transmit fifo write 1 to clear transmit fifo, internal poi nter is reset to fifo start point, and txfifo_level[3:0] returns to zero and transmit fifo becomes empty but data in transmit fifo is not changed. this bit is clear by hardware automatically, read it return zero. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 474 - revision v1.06 [17] lchzcen left channel zero cross detect enable if this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then lzcf flag in i2s_status register is set to 1. 1 = enable left channel zero cross detect 0 = disable left channel zero cross detect [16] rchzcen right channel zero cross detect enable if this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then lzcf flag in i2s_status register is set to 1. 1 = enable right channel zero cross detect 0 = disable right channel zero cross detect [15] mclken master clock enable if numicro ? nuc100 series, external crystal clock is frequency 2*n*256fs then software can program mclk_div[2:0] in i2s_clkdiv register to get 256fs clock to audio codec chip. 1 = enable master clock 0 = disable master clock [14:12] rxth[2:0] receive fifo threshold level when received data word(s) in buffer is equ al or higher than threshold level then rxthi flag is set. 000 = 1 word data in receive fifo 001 = 2 word data in receive fifo 010 = 3 word data in receive fifo 011 = 4 word data in receive fifo 100 = 5 word data in receive fifo 101 = 6 word data in receive fifo 110 = 7 word data in receive fifo 111 = 8 word data in receive fifo [11:9] txth[2:0] transmit fifo threshold level if remain data word (32 bits) in transmit fifo is the same or less than threshold level then txthi flag is set. 000 = 0 word data in transmit fifo 001 = 1 word data in transmit fifo 010 = 2 words data in transmit fifo 011 = 3 words data in transmit fifo 100 = 4 words data in transmit fifo 101 = 5 words data in transmit fifo 110 = 6 words data in transmit fifo 111 = 7 words data in transmit fifo numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 475 - revision v1.06 [8] slave slave mode i 2 s can operate as master or slave. for ma ster mode, i2s_bclk and i2s_lrclk pins are output mode and send bit clock from numicro ? nuc100 series to audio codec chip. in slave mode, i2s_bclk and i2s_lrclk pins are input mode and i2s_bclk and i2s_lrclk signals are received from outer audio codec chip. 1 = slave mode 0 = master mode [7] format data format 1 = msb justified data format 0 = i 2 s data format [6] mono monaural data 1 = data is monaural format 0 = data is stereo format [5:4] wordwidth word width 00 = data is 8 bit 01 = data is 16 bit 10 = data is 24 bit 11 = data is 32 bit [3] mute transmit mute enable 1= transmit channel zero 0 = transmit data is shifted from buffer [2] rxen receive enable 1 = enable data receive 0 = disable data receive [1] txen transmit enable 1 = enable data transmit 0 = disable data transmit [0] i2sen enable i 2 s controller 1 = enable 0 = disable numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 476 - revision v1.06 i 2 s clock divider (i2s_clkdiv) register offset r/w description reset value i2s_clkdiv i2s_ba+0x04 r/w i 2 s clock divider control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 bclk_div [7:0] 7 6 5 4 3 2 1 0 reserved mclk_div[2:0] bits descriptions [31:16] reserved reserved [15:8] bclk_div [7:0] bit clock divider if i 2 s operates in master mode, bit clock is provided by numicro ? nuc100 series. software can program these bits to generate sampling rate clock frequency. f_bclk = f_i2sclk /(2x(bclk_div + 1)) [7:3] reserved reserved [2:0] mclk_div[2:0] master clock divider if chip external crystal frequency is (2xmclk_div)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. if mclk_div is set to 0, mclk is the same as external clock input. for example, sampling rate is 24 khz and chip external crystal clock is 12.288 mhz, set mclk_div=1. f_mclk = f_i2sclk/(2x(mclk_div)) (when mclk_div is >= 1 ) f_mclk = f_i2sclk (when mclk_div is set to 0 ) numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 477 - revision v1.06 i 2 s interrupt enable register (i2s_ie) register offset r/w description reset value i2s_ie i2s_ba+0x08 r/w i 2 s interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved lzcie rzcie txthie txovfie txudfie 7 6 5 4 3 2 1 0 reserved rxthie rxovfie rxudfie bits descriptions [31:13] reserved reserved [12] lzcie left channel zero cross interrupt enable interrupt occur if this bit is set to 1 and left channel zero cross 1 = enable interrupt 0 = disable interrupt [11] rzcie right channel zero cross interrupt enable 1 = enable interrupt 0 = disable interrupt [10] txthie transmit fifo threshold level interrupt enable interrupt occurs if this bit is set to 1 and data words in transmit fifo is less than txth[2:0]. 1 = enable interrupt 0 = disable interrupt [9] txovfie transmit fifo overflow interrupt enable interrupt occurs if this bit is set to 1 and transmit fifo overflow flag is set to 1 1 = enable interrupt 0 = disable interrupt [8] txudfie transmit fifo underflow interrupt enable interrupt occur if this bit is set to 1 and transmit fifo underflow flag is set to 1. 1 = enable interrupt 0 = disable interrupt [7:3] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 478 - revision v1.06 [2] rxthie receive fifo threshold level interrupt enable when data word in receive fifo is equal or higher then rxth[2:0] and the rxthi bit is set to 1. if rxthie bit is enabled, interrupt occur. 1 = enable interrupt 0 = disable interrupt [1] rxovfie receive fifo overflow interrupt enable 1 = enable interrupt 0 = disable interrupt [0] rxudfie receive fifo underflow interrupt enable if software read receive fifo when it is empty then rxudf flag in i2sstatus register is set to 1. 1 = enable interrupt 0 = disable interrupt numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 479 - revision v1.06 i 2 s status register (i2s_status) register offset r/w description reset value i2s_status i2s_ba+0x0c r/w i 2 s status register 0x0014_1000 31 30 29 28 27 26 25 24 tx_level[3:0] rx_level[3:0] 23 22 21 20 19 18 17 16 lzcf rzcf txbusy txempty txfull txthf txovf txudf 15 14 13 12 11 10 9 8 reserved rxempty rxfull rxthf rxovf rxudf 7 6 5 4 3 2 1 0 reserved right i2stxint i2srxint i2sint bits descriptions [31:28] tx_level transmit fifo level these bits indicate word number in transmit fifo 0000 = no data 0001 = 1 word in transmit fifo ?. 1000 = 8 words in transmit fifo [27:24] rx_level receive fifo level these bits indicate word number in receive fifo 0000 = no data 0001 = 1 word in receive fifo ?. 1000 = 8 words in receive fifo [23] lzcf left channel zero cross flag it indicates left channel next sample data sign bit is changed or all data bits are zero. 1 = left channel zero cross is detected 0 = no zero cross software can write 1 to clear this bit to zero [22] rzcf right channel zero cross flag it indicates right channel next sample data si gn bit is changed or all data bits are zero. 1 = right channel zero cross is detected 0 = no zero cross software can write 1 to clear this bit to zero numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 480 - revision v1.06 [21] txbusy transmit busy this bit is clear to 0 when all data in trans mit fifo and shift buffer is shifted out. and set to 1 when 1st data is load to shift buffer. 1 = transmit shift buffer is busy 0 = transmit shift buffer is empty this bit is read only. [20] txempty transmit fifo empty this bit reflect data word number in transmit fifo is zero 1 = empty 0 = not empty this bit is read only. [19] txfull transmit fifo full this bit reflect data word number in transmit fifo is 8 1 = full. 0 = not full. this bit is read only [18] txthf transmit fifo threshold flag when data word(s) in transmit fifo is equal or lower than threshold value set in txth[2:0] the txthf bit becomes to 1. it keeps at 1 till txfifo_level[3:0] is higher than txth[1:0] after software write txfifo register. 1 = data word(s) in fifo is equal or lower than threshold level 0 = data word(s) in fifo is higher than threshold level this bit is read only [17] txovf transmit fifo overflow flag write data to transmit fifo when it is full and this bit set to 1 1 = overflow 0 = no overflow software can write 1 to clear this bit to zero [16] txudf transmit fifo underflow flag when transmit fifo is empty and shift logic hardware read data from data fifo causes this set to 1. 1 = underflow 0 = no underflow software can write 1 to clear this bit to zero [15:13] reserved reserved [12] rxempty receive fifo empty this bit reflects data words num ber in receive fifo is zero 1 = empty 0 = not empty this bit is read only. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 481 - revision v1.06 [11] rxfull receive fifo full this bit reflect data words number in receive fifo is 8 1 = full 0 = not full this bit is read only. [10] rxthf receive fifo threshold flag when data word(s) in receive fifo is equal or higher than threshold value set in rxth[2:0] the rxthf bit becomes to 1. it keeps at 1 till rxfifo_level[3:0] less than rxth[1:0] after software read rxfifo register. 1 = data word(s) in fifo is equal or higher than threshold level 0 = data word(s) in fifo is lower than threshold level this bit is read only [9] rxovf receive fifo overflow flag when receive fifo is full and receive hardware attempt write to data into receive fifo then this bit is set to 1, data in 1st buffer is overwrote. 1 = overflow occur 0 = no overflow occur software can write 1 to clear this bit to zero [8] rxudf receive fifo underflow flag read receive fifo when it is empty, this bit set to 1 indicate underflow occur. 1 = underflow occur 0 = no underflow occur software can write 1 to clear this bit to zero [7:4] reserved reserved [3] right right channel this bit indicate current trans mit data is belong to right channel 1 = right channel 0 = left channel this bit is read only [2] i2stxint i 2 s transmit interrupt 1 = transmit interrupt 0 = no transmit interrupt this bit is read only [1] i2srxint i 2 s receive interrupt 1 = receive interrupt 0 = no receive interrupt this bit is read only numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 482 - revision v1.06 [0] i2sint i 2 s interrupt flag 1 = i 2 s interrupt 0 = no i 2 s interrupt it is wire-or of i2stxint and i2srxint bits. this bit is read only. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 483 - revision v1.06 i 2 s transmit fifo (i2s_txfifo) register offset r/w description reset value i2s_txfifo i2s_ba+0x10 r/w i 2 s transmit fifo 0x0000_0000 31 30 29 28 27 26 25 24 txfifo[31:24] 23 22 21 20 19 18 17 16 txfifo[23:16] 15 14 13 12 11 10 9 8 txfifo[15:8] 7 6 5 4 3 2 1 0 txfifo[7:0] bits descriptions [31:0] txfifo transmit fifo register i 2 s contains 8 words (8x32 bit) data buffer fo r data transmit. write data to this register to prepare data for transmit. the remain wo rd number is indicated by tx_level[3:0] in i2s_status numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 484 - revision v1.06 i 2 s receive fifo (i2s_rxfifo) register offset r/w description reset value i2s_rxfifo i2s_ba+0x14 r/w i 2 s receive fifo 0x0000_0000 31 30 29 28 27 26 25 24 rxfifo[31:24] 23 22 21 20 19 18 17 16 rxfifo[23:16] 15 14 13 12 11 10 9 8 rxfifo[15:8] 7 6 5 4 3 2 1 0 rxfifo[7:0] bits descriptions [31:0] rxfifo receive fifo register i 2 s contains 8 words (8x32 bit) data buffer fo r data receive. read this register to get data in fifo. the remaining data word number is indicated by rx_level[3:0] in i2s_status register. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 485 - revision v1.06 5.16 analog-to-digital converter (adc) 5.16.1 overview numicro ? nuc100 series contains one 12-bit successive approximation analog-to-digital converters (sar a/d converter) with 8 i nput channels. the a/d converter supports three operation modes: single, single-cycle scan and c ontinuous scan mode. there are two kinds of scan mode: continuous mode and single cycle mode. the a/d converters can be started by software and external stadc pin. 5.16.2 features z analog input voltage range: 0~vref (max to 5.0v) z 12-bit resolution and 10-bit accuracy is guaranteed z up to 8 single-end analog input channels or 4 differential analog input channels z maximum adc clock frequency is 16mhz z up to 600k sps conversion rate z three operating modes ? single mode: a/d conversion is performed one time on a specified channel ? single-cycle scan mode: a/d conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel ? continuous scan mode: a/d converter conti nuously performs single-cycle scan mode until software stops a/d conversion z an a/d conversion can be started by ? software write 1 to adst bit ? external pin stadc z conversion results are held in data registers for each channel with valid and overrun indicators z conversion result can be compared with spec ify value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting z channel 7 supports 3 input sources: external analog voltage, internal fixed bandgap voltage, and internal temperature sensor output z support self-calibration to minimize conversion error numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 486 - revision v1.06 5.16.3 block diagram 12-bit dac & calibration a/d status register (adstr) analog control logics successive approximations register a/d data register 0 (addr0) a/d data register 1 (addr1) a/d data register 7 (addr7) : . + - digatal control logics & adc clock generator a/d control register (adcr) a/d channel enable register (adcher) a/d compare register (adcmr) a/d calibration rgister (adcalr) ... ain[0] ain[1] ain[7] * 8 to 1 analog mux sample and hold comparator pdma request rslt[11:0] adint stadc analog macro adc clock and adc start signal vref adc channel select apb bus valid & overrun adf * ain[7] source is selected by presel[1:0] adc7 vbg 00 01 presel[1:0] vtemp reserved 10 11 adc conversion finish and adc calibration finish signal figure 5-94 adc controller block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 487 - revision v1.06 5.16.4 functional description the a/d converter operates by successive approximation with 12-bit resolution. this a/d converter equips with self calibration function to minimum conversion error, user can write 1 to calen bit in adcalr register to enable calibration fu nction, while internal calibration is finish the cal_done bit will assert. the adc has three operation modes: single mode, single-cycle scan mode and continuous scan mode. when changing the operating mode or analog input channel enable, in order to prevent incorrect operation, software must clear adst bit to 0 in adcr register. 5.16.4.1 self-calibration whe n chip power on or switch adc input type between single-end input and differential input, it needs to do adc self calibration to minimize the conversion error. user can write 1 to calen bit in adcalr register to enable self calibration. t he operation is process internally and it needs 127 adc clocks to complete calibration. after calen is set to 1, software must wait cal_done bit set by internal hardware. the detail timing is shown as below: cal_en cal_done 1 2 127 adc_clk figure 5-95 adc converter self-calibration timing diagram 5.16.4.2 adc clock generator the maximum sampling rate is up to 600k sps. the adc engine has three clock sources selected by 2-bit adc_s (clksel[3:2]), the adc clock frequency is divided by an 8-bit prescaler with the formula: the adc clock frequency = (adc clock source frequency) / (adc_n+1); where the 8-bit adc_n is located in register clkdiv[23:16]. in generally, software can set adc_s and adc_n to get 16mhz or slightly less. because the bandgap voltage source lacks the drivin g capability, a conversion rate lower than 15 khz (@5v) is recommended. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 488 - revision v1.06 figure 5-96 adc clock control 5.16.4.3 single mode in single mo de, a/d conversion is performed only once on the specified single channel. the operations are as follows: 1. a/d conversion is started when the adst bit in adcr is set to 1 by software or external trigger input. 2. when a/d conversion is finished, the re sult is stored in the a/d data register corresponding to the channel. 3. on completion of conversion, the adf bi t in adsr is set to 1 and adc interrupt (adc_int) is requested if the adie bit is set to 1. 4. the adst bit remains 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters idle state. note: if software enables more than one channel in single mode, the least channel is converted and other enabled channels will be ignored. sample adst adf 1 29 820 addrx[11:0] adc_clk addrx[11:0] figure 5-97 single mode conversion timing diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 489 - revision v1.06 5.16.4.4 single-cycle scan mode in singl e-cycle scan mode, a/d conversion will sa mple and convert the specified channels once in the sequence from the least to highest channel. operations are as follows: 1. when the adst bit in adcr is set to 1 by a software or external trigger input, a/d conversion starts on the channel with the lowest number. 2. when a/d conversion for each enabled channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the enabled channels is completed, the adf bit in adsr is set to 1. if the adie bit is set to 1 at this time , an adc_int interrupt is requested after a/d conversion ends. 4. after a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters idle state. if adst is cleared to 0 before all enabled adc channels conversion done, adc controller will finish current conversion and the result of the lowest enabled adc channel will become unpredictable. an example timing diagram for single-cycle scan on e nabled channels (0, 2, 3 and 7) is shown as below: figure 5-98 single-cycle scan on enabled channels timing diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 490 - revision v1.06 5.16.4.5 continuous scan mode in contin uous scan mode, a/d conversion is performed sequentially on the specified channels that enabled by chen bits in adcher register (maximum 8 channels for adc). the operations are as follows: 1. when the adst bit in adcr is set to 1 by software or external trigger input, a/d conversion starts on the channel with the lowest number. 2. when a/d conversion for each enabled channel is completed, the result of each enabled channel is stored in the a/d data register corresponding to each enabled channel. 3. when all enabled channel sequentially completes a/d converting once, the adf bit (adsr[0]) will be set to 1. if the adie bit is set to 1 at this time, an adc_int interrupt is requested after a/d conversion ends. conversion of the 1st enabled channel starts again. 4. steps 2 to 3 are repeated as long as the adst bit remains enable. when adst is cleared to 0, adc controller will finish current conversion and the result of the lowest enabled adc channel will become unpredictable. an example timing diagram for continuous scan on enabled channels (0, 2, 3 and 7) is shown as below: figure 5-99 continuous scan on enabled channels timing diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 491 - revision v1.06 5.16.4.6 input sampling and a/d conversion time a/d conversi on can be triggered by external pin re quest. when the adcr.trgen is set to high to enable adc external trigger function, setting the trgs[1:0] bits to 00b is to select external trigger input from the stadc pin. software can se t trgcond[1:0] to select trigger condition is falling/rising edge or low/high level. an 8-bit sampling counter is used to deglitch. if level trigger condition is selected, the stadc pin must be kept at defined state at least 8 pclks. the adst bit will be set to 1 at the 9th pclk and start to conversion. conversion is continuous if external trigger input is pull at low (or high state) in level trigger mode. it is stopped only when external condition trigger condition disappears. if edge trigger condition is selected, the high and low state must be kept at least 4 plcks. pulse that is shorter than this specification will be ignored. adc external trigger function is only su pported at single-cycle scan mode. 5.16.4.7 conversion result monitor by compare mode adc controller provide two sets of compare register adcmpr0 and 1 to monitor maximum two specified channels conversion result from a/d conversion controller, refer to figure 5-100. software can select which channel to be m onitored by set cmpch(adcmprx[5:0]) and cmpcond bit is used to check co nversion result is less than spec ify value or greater than (equal to) value specified in cmpd[11:0]. when the c onversion of the channel specified by cmpch is completed, the comparing action will be triggered one time automatically. when the compare result meets the setting, compare match counter will increase 1, otherwise, the compare match counter will be clear to 0. when counter value reach the setting of (cmpmatcnt+1) then cmpf bit will be set to 1, if cmpie bit is set then an adc_int interrupt request is generated. software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. detail logics diagram is shown as below: 8 to 1 analog mux figure 5-100 a/d conversion result monitor logics diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 492 - revision v1.06 5.16.4.8 interrupt sources the a/d co nverter generates a conversion end adf in adsr register upon the end of a/d conversion. if adie bit in adcr is set then conversion end interrupt request adc_int is generated. if cmpie bit is enabled, when a/ d conversion result me ets setting in adcmpr register, monitor interrupt is generated, adc_int will be set also. cpu can clear cmpf and adf to stop interrupt request. figure 5-101 a/d controller interrupt 5.16.4.9 peripheral dma request whe n a/d conversion is finished, the conversion result will be loaded into addr register and valid bit will be set to 1. if the pten bit of adcr is set, adc controller will generate a request to pdma. user can use pdma to transfer the conversi on results to a user-specified memory space without cpu's intervention. the source address of pdma operation is fixed at adpdma, no matter what channels was selected. when pdma is transferring the conversion result, adc will continue converting the next selected channel if the operation mode of adc is single scan mode or continuous scan mode. user can monitor current pdma transfer data through reading adpdma register. if adc completes the conversion of a selected channel and the last conversion result of the same channel has not been transfe rred by pdma, overun bit of the corresponding channel will be set and the last adc conversion result will be overwrite by the new adc conversion result. pdma will transfer the latest data of selected channels to the user-specified destination address. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 493 - revision v1.06 5.16.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value adc_ba = 0x400e_0000 addr0 adc_ba+0x00 r a/d data register 0 0x0000_0000 addr1 adc_ba+0x04 r a/d data register 1 0x0000_0000 addr2 adc_ba+0x08 r a/d data register 2 0x0000_0000 addr3 adc_ba+0x0c r a/d data register 3 0x0000_0000 addr4 adc_ba+0x10 r a/d data register 4 0x0000_0000 addr5 adc_ba+0x14 r a/d data register 5 0x0000_0000 addr6 adc_ba+0x18 r a/d data register 6 0x0000_0000 addr7 adc_ba+0x1c r a/d data register 7 0x0000_0000 adcr adc_ba+0x20 r/w a/d control register 0x0000_0000 adcher adc_ba+0x24 r/w a/d channel enable register 0x0000_0000 adcmpr0 adc_ba+0x28 r/w a/d compare register 0 0x0000_0000 adcmpr1 adc_ba+0x2c r/w a/d compare register 1 0x0000_0000 adsr adc_ba+0x30 r/w a/d status register 0x0000_0000 adcalr adc_ba+0x34 r/w a/d calibration register 0x0000_0000 adpdma adc_ba+0x40 r adc pdma current transfer data 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 494 - revision v1.06 5.16.6 register description a/d data registers (addr0 ~ addr7) register offset r/w description reset value addr0 adc_ba+0x00 r a/d data register 0 0x0000_0000 addr1 adc_ba+0x04 r a/d data register 1 0x0000_0000 addr2 adc_ba+0x08 r a/d data register 2 0x0000_0000 addr3 adc_ba+0x0c r a/d data register 3 0x0000_0000 addr4 adc_ba+0x10 r a/d data register 4 0x0000_0000 addr5 adc_ba+0x14 r a/d data register 5 0x0000_0000 addr6 adc_ba+0x18 r a/d data register 6 0x0000_0000 addr7 adc_ba+0x1c r a/d data register 7 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved valid overrun 15 14 13 12 11 10 9 8 rslt [15:8] 7 6 5 4 3 2 1 0 rslt[7:0] bits descriptions [31:18] reserved reserved [17] valid valid flag 1 = data in rslt[15:0] bits is valid 0 = data in rslt[15:0] bits is not valid this bit is set to 1 when corresponding c hannel analog input conversion is completed and cleared by hardware after addr register is read. this is a read only bit numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 495 - revision v1.06 [16] overrun over run flag 1 = data in rslt[15:0] is overwrite 0 = data in rslt[15:0] is recent conversion result if converted data in rslt[15:0] has not been read before new conversion result is loaded to this register, overrun is set to 1 and previous conversion result is gone. it is cleared by hardware after addr register is read. this is a read only bit [15:0] rslt a/d conversion result this field contains conv ersion result of adc. for medium density, rslt[15:12] always read as 0. the following description is only support in low density: when dmof bit (adcr[31]) set to 0, 12 bits adc conversion result with unsigned format will be filled in rslt[11:0] and zero will be filled in rslt[15:12]. when dmof bit (adcr[31]) set to 1, 12 bits adc conversion result with 2?complement format will be filled in rslt[11:0] and signed bits to will be filled in rslt[15:12]. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 496 - revision v1.06 figure 5-102 adc single-end input conversion vo ltage and conversion result mapping diagram 0000_0000_0000 adc result in rslt[11:0] (dmof = 0) 0000_0000_0001 0000_0000_0010 1111_1111_1111 1111_1111_1110 1111_1111_1101 -vref + 1 lsb vref - 1 lsb differential input voltage vdiff (v) 1000_0000_0001 1000_0000_0000 0111_1111_1111 0 1 lsb = vref/4096 1111_1000_0000_0000 adc result in rslt[15:0] (dmof = 1) 1111_1000_0000_0001 1111_1000_0000_0010 0000_0111_1111_1111 0000_0111_1111_1110 0000_0111_1111_1101 -vref + 1 lsb vref - 1 lsb differential input voltage vdiff (v) 0000_0000_0000_0001 0000_0000_0000_0000 1111_1111_1111_1111 0 1 lsb = vref/4096 note: vref voltage comes from avdd for 64/48/36-pin package note: vref voltage comes from avdd for 64/48/36-pin package figure 5-103 adc differential input conversion voltage and conversion result mapping diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 497 - revision v1.06 a/d control register (adcr) register offset r/w description reset value adcr adc_ba+0x20 r/w adc control register 0x0000_0000 31 30 29 28 27 26 25 24 dmof reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved adst diffen pten trgen 7 6 5 4 3 2 1 0 trgcond trgs admd adie aden bits descriptions [31] dmof a/d differential input mode output format (this bit is only support in low density) 1 = a/d conversion result will be filled in rslt at addrx registers with 2'complement format. 0 = a/d conversion result will be filled in rslt at addrx registers with unsigned format. [30:12] reserved reserved [11] adst a/d conversion start 1 = conversion start 0 = conversion stopped and a/d converter enter idle state adst bit can be set to 1 from two sources: software write and external pin stadc. adst is cleared to 0 by hardware automatic ally at the ends of single mode and single- cycle scan mode on specified channels. in c ontinuous scan mode, a/d conversion is continuously performed sequentially until software write 0 to this bit or chip reset. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 498 - revision v1.06 [10] diffen a/d differential input mode enable 1 = a/d is in differential analog input mode 0 = a/d is in single-end analog input mode adc analog input differential input paired channel v plus v minus 0 adc0 adc1 1 adc2 adc3 2 adc4 adc5 3 adc6 adc7 differential input voltage (v diff ) = v plus - v minus in differential input mode, only one of the two corresponding channels needs to be enabled in adcher. the conversion result will be placed to the corresponding data register of the enabled channel. if both channel s of a differential input paired channel are enabled, the adc will convert it twice in scan mode. and then write the conversion result to the two corresponding data registers. [9] pten pdma transfer enable 1 = enable pdma data transfer in addr 0~7 0 = disable pdma data transfer when a/d conversion is completed, the c onverted data is loaded into addr 0~7, software can enable this bit to generate a pdma data transfer request. when pten=1, software must set adie=0 to disable interrupt. [8] trgen external trigger enable enable or disable triggering of a/d conversion by external stadc pin. 1= enable 0= disable [7:6] trgcond external trigger condition these two bits decide external pin stadc tr igger event is level or edge. the signal must be kept at stable state at least 8 pclks for level trigger and 4 pclks at high and low state for edge trigger. 00 = low level 01 = high level 10 = falling edge 11 = rising edge [5:4] trgs hardware trigger source 00 = a/d conversion is started by external stadc pin. others = reserved software should disable trge n and adst before change trgs. in hardware trigger mode, the adst bit is set by the external trigger from stadc. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 499 - revision v1.06 [3:2] admd a/d converter operation mode 00 = single conversion 01 = reserved 10 = single-cycle scan 11 = continuous scan when changing the operation mode, software should disable adst bit firstly. [1] adie a/d interrupt enable 1 = enable a/d interrupt function 0 = disable a/d interrupt function a/d conversion end interrupt request is generated if adie bit is set to 1. [0] aden a/d converter enable 1 = enable 0 = disable before starting a/d conversion function, this bit should be set to 1. clear it to 0 to disable a/d converter analog circuit for saving power consumption. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 500 - revision v1.06 a/d channel enable register (adcher) register offset r/w description reset value adcher adc_ba+0x24 r/w a/d channel enable 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved presel[1:0] 7 6 5 4 3 2 1 0 chen7 chen6 chen5 chen4 chen3 chen2 chen1 chen0 bits descriptions [31:10] reserved reserved [9:8] presel analog input channel 7 select 00 = external analog input 01 = internal bandgap voltage 10 = internal temperature sensor 11 = reserved [7] chen7 analog input channel 7 enable 1 = enable 0 = disable [6] chen6 analog input channel 6 enable 1 = enable 0 = disable [5] chen5 analog input channel 5 enable 1 = enable 0 = disable [4] chen4 analog input channel 4 enable 1 = enable 0 = disable [3] chen3 analog input channel 3 enable 1 = enable 0 = disable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 501 - revision v1.06 [2] chen2 analog input channel 2 enable 1 = enable 0 = disable [1] chen1 analog input channel 1 enable 1 = enable 0 = disable [0] chen0 analog input channel 0 enable 1 = enable 0 = disable note: channel0 is the default enable channel if chen0~7 are set as 0s. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 502 - revision v1.06 a/d compare register 0/1 (adcmpr0/1) register offset r/w description reset value adcmpr0 adc_ba+0x28 r/w a/d compare register 0 0x0000_0000 adcmpr1 adc_ba+0x2c r/w a/d compare register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved cmpd[11:8] 23 22 21 20 19 18 17 16 cmpd[7:0] 15 14 13 12 11 10 9 8 reserved cmpmatcnt 7 6 5 4 3 2 1 0 reserved cmpch cmpcond cmpie cmpen bits descriptions [31:28] reserved reserved [27:16] cmpd comparison data the 12 bits data is used to compare with conversion result of specified channel. software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. the following description is only support in low density: when dmof bit is set to 0, adc comparator compares cmpd with conversion result with unsigned format. cmpd should be filled in unsigned format. when dmof bit is set to 1, adc comparator compares cmpd with conversion result with 2?complement format. cmpd should be filled in 2?complement format. [15:12] reserved reserved [11:8] cmpmatcnt compare match count when the specified a/d channel analog c onversion result matches the compare condition defined by cmpcond[2], the intern al match counter will increase 1. when the internal counter reaches the value to (cmpmatcnt +1), the cmpfx bit will be set. [7:6] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 503 - revision v1.06 [5:3] cmpch compare channel selection 000 = channel 0 conversion result is selected to be compared 001 = channel 1 conversion result is selected to be compared 010 = channel 2 conversion result is selected to be compared 011 = channel 3 conversion result is selected to be compared 100 = channel 4 conversion result is selected to be compared 101 = channel 5 conversion result is selected to be compared 110 = channel 6 conversion result is selected to be compared 111 = channel 7 conversion result is selected to be compared [2] cmpcond compare condition 1 = set the compare condition as that when a 12-bit a/d conversion result is greater or equal to the 12-bit cmpd (adcmprx[27:16]), the internal match counter will increase one. 0 = set the compare condition as that when a 12-bit a/d conversion result is less than the 12-bit cmpd (adcmprx[27:16]), the internal match counter will increase one. note: when the internal counter reaches the value to (cmpmatcnt +1), the cmpfx bit will be set. [1] cmpie compare interrupt enable 1 = enable compare function interrupt 0 = disable compare function interrupt if the compare function is enabled and the compare condition matches the setting of cmpcond and cmpmatcnt, cmpf bit will be asserted, in the meanwhile, if cmpie is set to 1, a compare interrupt request is generated. [0] cmpen compare enable 1 = enable compare 0 = disable compare set this bit to 1 to enable adc controller to compare cmpd[11:0] with specified channel conversion result when convert ed data is loaded into addr register. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 504 - revision v1.06 a/d status register (adsr) register offset r/w description reset value adsr adc_ba+0x30 r/w adc channel selection enable register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 overrun 15 14 13 12 11 10 9 8 valid 7 6 5 4 3 2 1 0 reserved channel busy cmpf1 cmpf0 adf bits descriptions [31:24] reserved reserved [23:16] overrun over run flag it is a mirror to overrun bit in addrx it is read only. [15:8] valid data valid flag it is a mirror of valid bit in addrx it is read only. [7] reserved reserved [6:4] channel current conversion channel this field reflects current conversion channel when busy=1. when busy=0, it shows the next channel will be converted. it is read only. [3] busy busy/idle 1 = a/d converter is busy at conversion. 0 = a/d converter is in idle state. this bit is mirror of as adst bit in adcr. it is read only. [2] cmpf1 compare flag when the selected channel a/d conversion result meets setting condition in adcmpr1 then this bit is set to 1. a nd it is cleared by writing 1 to self. 1 = conversion result in addr meets adcmpr1 setting 0 = conversion result in addr does not meet adcmpr1 setting numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 505 - revision v1.06 [1] cmpf0 compare flag when the selected channel a/d conversion result meets setting condition in adcmpr0 then this bit is set to 1. a nd it is cleared by writing 1 to self. 1 = conversion result in addr meets adcmpr0 setting 0 = conversion result in addr does not meet adcmpr0 setting [0] adf a/d conversion end flag a status flag that indicates the end of a/d conversion. adf is set to 1 at these two conditions: 1. when a/d conversion ends in single mode 2. when a/d conversion ends on all specified channels in scan mode this flag can be cleared by writing 1 to self. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 506 - revision v1.06 a/d calibration register (adcalr) register offset r/w description reset value adcalr adc_ba+0x34 r/w a/d calibration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved caldone calen bits descriptions [31:2] reserved reserved [1] caldone calibration is done 1 = a/d converter self calibration is done 0 = a/d converter has not been calibrated or ca libration is in progress if calen bit is set. when 0 is written to calen bit, caldone bit is cleared by hardware immediately. it is a read only bit. [0] calen self calibration enable 1 = enable self calibration 0 = disable self calibration software can set this bit to 1 enables a/d conv erter to do self calibration function. it needs 127 adc clocks to complete calibrati on. this bit must be kept at 1 after caldone asserted. clearing this bit w ill disable self calibration function. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 507 - revision v1.06 a/d pdma current transfer data register (adpdma) register offset r/w description reset value adpdma adc_ba+0x40 r a/d pdma current transfer data register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved ad_pdma[11:8] 7 6 5 4 3 2 1 0 ad_pdma[7:0] bits descriptions [31:12] reserved reserved [11:0] ad_pdma adc pdma current transfer data register when pdma transferring, read this register can monitor current pdma transfer data. this is a read only register. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 508 - revision v1.06 5.17 analog comparator (cmp) 5.17.1 overview numicro ? nuc100 series contains two comparators. the comparators can be used in a number of different configurations. the comparator output is a logical one when positive input greater than negative input, otherwise the output is a zero. each comparator can be configured to cause an interrupt when the comparator output value changes. the block diagram is shown in figure 5-10 4. note that the analog input port pins must be configured as input type before analog comparator function is enabled. 5.17.2 features z analog input voltage range: 0~5.0v z hysteresis function supported z two analog comparators with optional internal reference voltage input at negative end z one comparator interrupt requested by either comparator numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 509 - revision v1.06 5.17.3 block diagram comp status register (cmpsr) + - digital control logics pc.7/cpn0 internal reference voltage = 1.2v analog input switch comparator 1 comparator interrupt pc.6/cpp0 compf0, cmpf1 comparator 0 cmpsr[co0] pc.14/cpp1 pc.15/cpn1 cn0,cn1 cmp0_hysen,cmp0en cmp1_hysen,cmp1en cmp0cr[cn0] 0 1 cmp1cr[cn1] cmpsr[co1] comp control registers (cmp0cr, cmp1cr) apb bus 0 1 + - pb.12/cpo0 pb.13/cpo1 co0, co1 figure 5-104 analog comparator block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 510 - revision v1.06 5.17.4 functional description 5.17.4.1 interrupt sources the comparator generates an output co1 (co2) in cmpsr register which is sampled by pclk. if cmp0ie (cmp1ie) bit in cmp0cr (cmp1cr) is set then a state change on the comparator output co0 (co1) will cause comparator flag cmpf0 (cmpf1) is set and the comparator interrupt is requested. software can write a zero to cmp0 and cmpf1 to stop interrupt request. figure 5-105 comparator c ontroller interrupt sources numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 511 - revision v1.06 5.17.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value cmp_ba = 0x400d_0000 cmp0cr cmp_ba+0x00 r/w comparator0 control register 0x0000_0000 cmp1cr cmp_ba+0x04 r/w comparator1 control register 0x0000_0000 cmpsr cmp_ba+0x08 r/w comparator status register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 512 - revision v1.06 5.17.6 register description cmp0 control register (cmp0cr) register offset r/w description reset value cmp0cr cmp_ba+0x00 r/w comparator0 control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved cn0 reserved cmp0_hyse n cmp0ie cmp0en bits descriptions [31:5] reserved reserved [4] cn0 comparator0 negative input select 1 = the internal comparator reference voltage (vref=1.2v) is selected as the negative comparator input 0 = the comparator reference pin cpn0 is selected as the negative comparator input [3] reserved reserved [2] cmp0_hysen comparator0 hysteresis enable 1 = enable cmp0 hysteresis function at co mparator 0 that the typical range is 20mv. 0 = disable cmp0 hyster esis function (default). [1] cmp0ie comparator0 interrupt enable 1 = enable cmp0 interrupt function 0 = disable cmp0 interrupt function interrupt is generated if cmp0ie bit is se t to 1 after cmp0 conversion finished. [0] cmp0en comparator0 enable 1 = enable 0 = disable comparator output need wait 10 us stable time after cmp0en is set. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 513 - revision v1.06 cmp1 control register (cmp1cr) register offset r/w description reset value cmp1cr cmp_ba+0x04 r/w comparator1 control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved cn1 reserved cmp1_hyse n cmp1ie cmp1en bits descriptions [31:5] reserved reserved [4] cn1 comparator1 negative input select 1 = the internal comparator reference voltage (vref=1.2v) is selected as the negative comparator input 0 = the comparator reference pin cpn1 is selected as the negative comparator input [3] reserved reserved [2] cmp1_hysen comparator1 hysteresis enable 1 = enable comparator1 hysteresis function; the typical range is 20mv 0 = disable comparator1 hysteresis function (default) [1] cmp1ie comparator1 interrupt enable 1 = enable comparator1 interrupt function 0 = disable comparator1 interrupt function interrupt is generated if cmp1ie bit is se t to 1 after cmp1 conversion finished. [0] cmp1en comparator1 enable 1 = enable comparator1 0 = disable comparator1 comparator output need wait 10 us stable time after cmp1en is set. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 514 - revision v1.06 cmp status register (cmpsr) register offset r/w description reset value cmpsr cmp_ba+0x08 r/w comparator channel selection enable register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved co1 co0 cmpf1 cmpf0 bits descriptions [31:4] reserved reserved [3] co1 comparator1 output synchronized to the apb clock to allow reading by software. cleared when the comparator is disabled (cmp1en = 0). [2] co0 comparator0 output synchronized to the apb clock to allow reading by software. cleared when the comparator is disabled (cmp0en = 0). [1] cmpf1 comparator1 flag this bit is set by hardware whenever the comparator1 output changes state. this will cause an interrupt if cmp1ie set. write 1 to clear this bit to zero. [0] cmpf0 comparator0 flag this bit is set by hardware whenever the comparator0 output changes state. this will cause an interrupt if cmp0ie set. write 1 to clear this bit to zero. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 515 - revision v1.06 5.18 pdma controller (pdma) 5.18.1 overview numicro ? nuc100 medium density contains a perip heral direct memory access (pdma) controller that transfers data to and from memo ry or transfer data to and from apb devices. the pdma has nine channels of dma (peripheral-to-memory or memory-to-peripheral or memory-to- memory). for each pdma channel (pdma ch0~ch8), there is one word buffer as transfer buffer between the peripherals apb devices and memory. software can stop the pdma operation by dis able pdma [pdmacen]. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. the pdma controller can increase source or destination address or fixed them as well. notice: numicro ? nuc100 low density only has 1 pdma channel (channel 0). 5.18.2 features z up to nine dma channels. each channel can support a unidirectional transfer (low density only has 1 pdma channel) z amba ahb master/slave interface compatible, for data transfer and register read/write z support source and destination address increased mode or fixed mode z hardware channel priority. dma channel has the highest priority and channel has the lowest priority numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 516 - revision v1.06 5.18.3 block diagram figure 5-106 medium density pdma controller block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 517 - revision v1.06 figure 5-107 low density pdma controller block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 518 - revision v1.06 5.18.4 function description the pdma controller has up to nine channels of dma associated with peripheral-to-memory memory-to-peripheral or memory-to-memory. for each pdma channel, there is one word memory as transfer buffer between the peripherals apb ip and memory. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. as to the source and destination address, the pdma controller has two modes: increased and fixed. every pdma default channel behavior is not pre-def ined, so users must configure the channel service settings of pdma_pdssr0 and pdma_pds sr1 before start the related pdma channel. software must enable dma channel pdma [pdmacen ] and then write a valid source address to the pdma_sarx register, a dest ination address to the pdma_dsabx register, and a transfer count to the pdma_bcrx register. next, trigger the dma_csrx pdma [trig_en]. pdma will continue the transfer until pdma_cbcrx comes down to zero, if an error occurs during the pdma operation, the channel stops unless software clears the error condition and sets the pdma_csrx [sw_rst] to reset the pdma channel and set pdma_csrx [pdmacen] and [trig_en] bits field to start again. in pdma (peripheral-to-memory or memory-to-pe ripheral) mode, dma can transfer data between the peripherals apb ip (ex: uart, spi, adc?.) and memory. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 519 - revision v1.06 5.18.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value pdma_ba_ch0 = 0x5000_8000 pdma_ba_ch1 = 0x5000_8100 pdma_ba_ch2 = 0x5000_8200 pdma_ba_ch3 = 0x5000_8300 pdma_ba_ch4 = 0x5000_8400 pdma_ba_ch5 = 0x5000_8500 pdma_ba_ch6 = 0x5000_8600 pdma_ba_ch7 = 0x5000_8700 pdma_ba_ch8 = 0x5000_8800 pdma_csrx pdma_ba_chx+0x00 r/w pdma control register 0x0000_0000 pdma_sarx pdma_ba_chx+0x04 r/w pdma source address register 0x0000_0000 pdma_darx pdma_ba_chx+0x08 r/w pdma destination address register 0x0000_0000 pdma_bcrx pdma_ba_chx+0x0c r/w pdma transfer byte count register 0x0000_0000 pdma_pointx pdma_ba_chx+0x10 r pdma internal buffer pointer 0xxxxx_0000 pdma_csarx pdma_ba_chx+0x14 r pdma current source address register 0x0000_0000 pdma_cdarx pdma_ba_chx+0x18 r pdma current destination address register 0x0000_0000 pdma_cbcrx pdma_ba_chx+0x1c r pdma current transfer byte count register 0x0000_0000 pdma_ierx pdma_ba_chx+0x20 r/w pdma interrupt enable register 0x0000_0001 pdma_isrx pdma_ba_chx+0x24 r/w pdma interrupt status register 0x0000_0000 pdma_sbuf0_cx pdma_ba_chx+0x80 r pdma shared buffer fifo 0 0x0000_0000 pdma_ba_gcr = 0x5000_8f00 pdma_gcrcsr pdma_ba_gcr+0x00 r/w pdma global control register 0x0000_0000 pdma_pdssr0 pdma_ba_gcr+0x04 r/w pdma service selection control register 0 0xffff_ffff pdma_pdssr1 pdma_ba_gcr+0x08 r/w pdma service select ion control register 1 0xffff_ffff pdma_gcrisr pdma_ba_gcr+0x0c r/w pdma global interrupt register 0x0000_0000 pdma_pdssr2 pdma_ba_gcr+0x10 r/w pdma service sele ction control register 2 0x0000_00ff notice: low density only support pdma channel 0. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 520 - revision v1.06 5.18.6 register description pdma control and status register (pdma_csrx) register offset r/w description reset value pdma_csr0 pdma_ba_ch0+0x00 r/w pdma control and status register ch0 0x0000_0000 pdma_csr1 pdma_ba_ch1+0x00 r/w pdma control and status register ch1 0x0000_0000 pdma_csr2 pdma_ba_ch2+0x00 r/w pdma control and status register ch2 0x0000_0000 pdma_csr3 pdma_ba_ch3+0x00 r/w pdma control and status register ch3 0x0000_0000 pdma_csr4 pdma_ba_ch4+0x00 r/w pdma control and status register ch4 0x0000_0000 pdma_csr5 pdma_ba_ch5+0x00 r/w pdma control and status register ch5 0x0000_0000 pdma_csr6 pdma_ba_ch6+0x00 r/w pdma control and status register ch6 0x0000_0000 pdma_csr7 pdma_ba_ch7+0x00 r/w pdma control and status register ch7 0x0000_0000 pdma_csr8 pdma_ba_ch8+0x00 r/w pdma control and status register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 trig_en reserved apb_tws reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 dad_sel sad_sel mode_ sel sw_rst pdmacen bits descriptions [31:24] reserved reserved [23] trig_en trig_en 1 = enable pdma data read or write transfer. 0 = no effect. note: when pdma transfer completed, this bit will be cleared automatically. if the bus error occurs, all pdma transfer will be stopped. software must reset all pdma channel, and then trigger again. [22:21] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 521 - revision v1.06 [20:19] apb_tws peripheral transfer width select 00 = one word (32 bits) is trans ferred for every pdma operation. 01 = one byte (8 bits) is trans ferred for every pdma operation. 10 = one half-word (16 bits) is transferred for every pdma operation. 11 = reserved. note: this field is meaningful only when mo de_sel is ip to memory mode (apb-to- memory) or memory to ip mode (memory-to-apb). [18:8] reserved reserved [7:6] dad_sel transfer destination address direction select 00 = transfer destination address is increasing successively. 01 = reserved. 10 = transfer destination address is fixed (this feature can be used when data where transferred from multiple sour ces to a single destination). 11 = reserved. [5:4] sad_sel transfer source address direction select 00 = transfer source address is increasing successively. 01 = reserved. 10 = transfer source address is fixed (this feature can be used when data where transferred from a single source to multiple destinations). 11 = reserved. [3:2] mode_sel pdma mode select 00 = memory to memory mode (memory-to-memory). 01 = ip to memory mode (apb-to-memory). 10 = memory to ip mode (memory-to-apb). [1] sw_rst software engine reset 0 = writing 0 to this bit has no effect. 1 = writing 1 to this bit will reset the inter nal state machine, pointers and internal buffer. the contents of control register will not be cleared. this bit will auto clear after few clock cycles. [0] pdmacen pdma channel enable setting this bit to 1 enables pdma?s operation. if this bit is cleared, pdma will ignore all pdma request and force bus master into idle state. note: sw_rst(pdma_csrx[1], x= 0~8) will clear this bit numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 522 - revision v1.06 pdma transfer source address register (pdma_sarx) register offset r/w description reset value pdma_sar0 pdma_ba_ch0+0x04 r/w pdma transfer s ource address register ch0 0x0000_0000 pdma_sar1 pdma_ba_ch1+0x04 r/w pdma transfer s ource address register ch1 0x0000_0000 pdma_sar2 pdma_ba_ch2+0x04 r/w pdma transfer s ource address register ch2 0x0000_0000 pdma_sar3 pdma_ba_ch3+0x04 r/w pdma transfer s ource address register ch3 0x0000_0000 pdma_sar4 pdma_ba_ch4+0x04 r/w pdma transfer s ource address register ch4 0x0000_0000 pdma_sar5 pdma_ba_ch5+0x04 r/w pdma transfer s ource address register ch5 0x0000_0000 pdma_sar6 pdma_ba_ch6+0x04 r/w pdma transfer s ource address register ch6 0x0000_0000 pdma_sar7 pdma_ba_ch7+0x04 r/w pdma transfer s ource address register ch7 0x0000_0000 pdma_sar8 pdma_ba_ch8+0x04 r/w pdma transfer s ource address register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 pdma_sar [31:24] 23 22 21 20 19 18 17 16 pdma_sar [23:16] 15 14 13 12 11 10 9 8 pdma_sar [15:8] 7 6 5 4 3 2 1 0 pdma_sar [7:0] bits descriptions [31:0] pdma_sar pdma transfer source address register this field indicates a 32-bit source address of pdma. note : the source address must be word alignment numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 523 - revision v1.06 pdma transfer destination address register (pdma_darx) register offset r/w description reset value pdma_dar0 pdma_ba_ch0+0x08 r/w pdma transfer dest ination address register ch0 0x0000_0000 pdma_dar1 pdma_ba_ch1+0x08 r/w pdma transfer dest ination address register ch1 0x0000_0000 pdma_dar2 pdma_ba_ch2+0x08 r/w pdma transfer dest ination address register ch2 0x0000_0000 pdma_dar3 pdma_ba_ch3+0x08 r/w pdma transfer dest ination address register ch3 0x0000_0000 pdma_dar4 pdma_ba_ch40x08 r/w pdma transfer destination address register ch4 0x0000_0000 pdma_dar5 pdma_ba_ch5+0x08 r/w pdma transfer dest ination address register ch5 0x0000_0000 pdma_dar6 pdma_ba_ch6+0x08 r/w pdma transfer dest ination address register ch6 0x0000_0000 pdma_dar7 pdma_ba_ch7+0x08 r/w pdma transfer dest ination address register ch7 0x0000_0000 pdma_dar8 pdma_ba_ch8+0x08 r/w pdma transfer dest ination address register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 pdma_dar [31:24] 23 22 21 20 19 18 17 16 pdma_dar [23:16] 15 14 13 12 11 10 9 8 pdma_dar [15:8] 7 6 5 4 3 2 1 0 pdma_dar [7:0] bits descriptions [31:0] pdma_dar pdma transfer destination address register this field indicates a 32-bi t destination address of pdma. note : the destination address must be word alignment numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 524 - revision v1.06 pdma transfer byte c ount register (pdma_bcrx) register offset r/w description reset value pdma_bcr0 pdma_ba_ch0+0x0c r/w pdma transfer byte count register ch0 0x0000_0000 pdma_bcr1 pdma_ba_ch1+0x0c r/w pdma transfer byte count register ch1 0x0000_0000 pdma_bcr2 pdma_ba_ch2+0x0c r/w pdma transfer byte count register ch2 0x0000_0000 pdma_bcr3 pdma_ba_ch3+0x0c r/w pdma transfer byte count register ch3 0x0000_0000 pdma_bcr4 pdma_ba_ch4+0x0c r/w pdma transfer byte count register ch4 0x0000_0000 pdma_bcr5 pdma_ba_ch5+0x0c r/w pdma transfer byte count register ch5 0x0000_0000 pdma_bcr6 pdma_ba_ch6+0x0c r/w pdma transfer byte count register ch6 0x0000_0000 pdma_bcr7 pdma_ba_ch7+0x0c r/w pdma transfer byte count register ch7 0x0000_0000 pdma_bcr8 pdma_ba_ch8+0x0c r/w pdma transfer byte count register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 pdma_bcr [15:8] 7 6 5 4 3 2 1 0 pdma_bcr [7:0] bits descriptions [31:16] reserved reserved [15:0] pdma_bcr pdma transfer byte count register this field indicates a 16-bit transfer byte count number of pdma, it must be word alignment. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 525 - revision v1.06 pdma internal buffer poin ter register (pdma_pointx) register offset r/w description reset value pdma_point0 pdma_ba_ch0+0x10 r pdma internal buffer pointer register ch0 0xxxxx_0000 pdma_point1 pdma_ba_ch1+0x10 r pdma internal buffer pointer register ch1 0xxxxx_0000 pdma_point2 pdma_ba_ch2+0x10 r pdma internal buffer pointer register ch2 0xxxxx_0000 pdma_point3 pdma_ba_ch3+0x10 r pdma internal buffer pointer register ch3 0xxxxx_0000 pdma_point4 pdma_ba_ch4+0x10 r pdma internal buffer pointer register ch4 0xxxxx_0000 pdma_point5 pdma_ba_ch5+0x10 r pdma internal buffer pointer register ch5 0xxxxx_0000 pdma_point6 pdma_ba_ch6+0x10 r pdma internal buffer pointer register ch6 0xxxxx_0000 pdma_point7 pdma_ba_ch7+0x10 r pdma internal buffer pointer register ch7 0xxxxx_0000 pdma_point8 pdma_ba_ch8+0x10 r pdma internal buffer pointer register ch8 0xxxxx_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pdma_point bits descriptions [31:2] reserved reserved [1:0] pdma_point pdma internal buffer pointer register (read only) this field indicates the internal buffer pointer. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 526 - revision v1.06 pdma current source address register (pdma_csarx) register offset r/w description reset value pdma_csar0 pdma_ba_ch0+0x14 r pdma current source address register ch0 0x0000_0000 pdma_csar1 pdma_ba_ch1+0x14 r pdma current source address register ch1 0x0000_0000 pdma_csar2 pdma_ba_ch2+0x14 r pdma current source address register ch2 0x0000_0000 pdma_csar3 pdma_ba_ch3+0x14 r pdma current source address register ch3 0x0000_0000 pdma_csar4 pdma_ba_ch4+0x14 r pdma current source address register ch4 0x0000_0000 pdma_csar5 pdma_ba_ch5+0x14 r pdma current source address register ch5 0x0000_0000 pdma_csar6 pdma_ba_ch6+0x14 r pdma current source address register ch6 0x0000_0000 pdma_csar7 pdma_ba_ch7+0x14 r pdma current source address register ch7 0x0000_0000 pdma_csar8 pdma_ba_ch8+0x14 r pdma current source address register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 pdma_csar [31:24] 23 22 21 20 19 18 17 16 pdma_csar [23:16] 15 14 13 12 11 10 9 8 pdma_csar [15:8] 7 6 5 4 3 2 1 0 pdma_csar [7:0] bits descriptions [31:0] pdma_csar pdma current source address register (read only) this field indicates the source address w here the pdma transfer is just occurring. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 527 - revision v1.06 pdma current destination address register (pdma_cdarx) register offset r/w description reset value pdma_cdar0 pdma_ba_ch0+0x18 r pdma current destination address register ch0 0x0000_0000 pdma_cdar1 pdma_ba_ch1+0x18 r pdma current destination address register ch1 0x0000_0000 pdma_cdar2 pdma_ba_ch2+0x18 r pdma current destination address register ch2 0x0000_0000 pdma_cdar3 pdma_ba_ch3+0x18 r pdma current destination address register ch3 0x0000_0000 pdma_cdar4 pdma_ba_ch4+0x18 r pdma current destination address register ch4 0x0000_0000 pdma_cdar5 pdma_ba_ch5+0x18 r pdma current destination address register ch5 0x0000_0000 pdma_cdar6 pdma_ba_ch6+0x18 r pdma current destination address register ch6 0x0000_0000 pdma_cdar7 pdma_ba_ch7+0x18 r pdma current destination address register ch7 0x0000_0000 pdma_cdar8 pdma_ba_ch8+0x18 r pdma current destination address register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 pdma_cdar [31:24] 23 22 21 20 19 18 17 16 pdma_cdar [23:16] 15 14 13 12 11 10 9 8 pdma_cdar [15:8] 7 6 5 4 3 2 1 0 pdma_cdar [7:0] bits descriptions [31:0] pdma_cdar pdma current destination address register (read only) this field indicates the destination address where the pdma transfer is just occurring. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 528 - revision v1.06 pdma current byte count register (pdma_cbcrx) register offset r/w description reset value pdma_cbcr0 pdma_ba_ch0+0x1c r pdma current byte count register ch0 0x0000_0000 pdma_cbcr1 pdma_ba_ch1+0x1c r pdma current byte count register ch1 0x0000_0000 pdma_cbcr2 pdma_ba_ch2+0x1c r pdma current byte count register ch2 0x0000_0000 pdma_cbcr3 pdma_ba_ch3+0x1c r pdma current byte count register ch3 0x0000_0000 pdma_cbcr4 pdma_ba_ch4+0x1c r pdma current byte count register ch4 0x0000_0000 pdma_cbcr5 pdma_ba_ch5+0x1c r pdma current byte count register ch5 0x0000_0000 pdma_cbcr6 pdma_ba_ch6+0x1c r pdma current byte count register ch6 0x0000_0000 pdma_cbcr7 pdma_ba_ch7+0x1c r pdma current byte count register ch7 0x0000_0000 pdma_cbcr8 pdma_ba_ch8+0x1c r pdma current byte count register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 pdma_cbcr [15:8] 7 6 5 4 3 2 1 0 pdma_cbcr [7:0] bits descriptions [31:16] reserved reserved [15:0] pdma_cbcr pdma current byte count register (read only) this field indicates the current remained byte count of pdma. note: sw_rst will clear this register value. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 529 - revision v1.06 pdma interrupt enable control register (pdma_ierx) register offset r/w description reset value pdma_ier0 pdma_ba_ch0+0x20 r/w pdma interrupt enable control register ch0 0x0000_0001 pdma_ier1 pdma_ba_ch1+0x20 r/w pdma interrupt enable control register ch1 0x0000_0001 pdma_ier2 pdma_ba_ch2+0x20 r/w pdma interrupt enable control register ch2 0x0000_0001 pdma_ier3 pdma_ba_ch3+0x20 r/w pdma interrupt enable control register ch3 0x0000_0001 pdma_ier4 pdma_ba_ch4+0x20 r/w pdma interrupt enable control register ch4 0x0000_0001 pdma_ier5 pdma_ba_ch5+0x20 r/w pdma interrupt enable control register ch5 0x0000_0001 pdma_ier6 pdma_ba_ch6+0x20 r/w pdma interrupt enable control register ch6 0x0000_0001 pdma_ier7 pdma_ba_ch7+0x20 r/w pdma interrupt enable control register ch7 0x0000_0001 pdma_ier8 pdma_ba_ch8+0x20 r/w pdma interrupt enable control register ch8 0x0000_0001 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved blkd_ie tabort_ie bits descriptions [31:2] reserved reserved [1] blkd_ie pdma transfer done interrupt enable 1 = enable interrupt generator during pdma transfer done. 0 = disable interrupt generator during pdma transfer done. [0] tabort_ie pdma read/write target abort interrupt enable 1 = enable target abort interrupt generation during pdma transfer. 0 = disable target abort interrupt generation during pdma transfer. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 530 - revision v1.06 pdma interrupt status register (pdma_isrx) register offset r/w description reset value pdma_isr0 pdma_ba_ch0+0x24 r/w pdma interrupt status register ch0 0x0x0x_0000 pdma_isr1 pdma_ba_ch1+0x24 r/w pdma interrupt status register ch1 0x0x0x_0000 pdma_isr2 pdma_ba_ch2+0x24 r/w pdma interrupt status register ch2 0x0x0x_0000 pdma_isr3 pdma_ba_ch3+0x24 r/w pdma interrupt status register ch3 0x0x0x_0000 pdma_isr4 pdma_ba_ch4+0x24 r/w pdma interrupt status register ch4 0x0x0x_0000 pdma_isr5 pdma_ba_ch5+0x24 r/w pdma interrupt status register ch5 0x0x0x_0000 pdma_isr6 pdma_ba_ch6+0x24 r/w pdma interrupt status register ch6 0x0x0x_0000 pdma_isr7 pdma_ba_ch7+0x24 r/w pdma interrupt status register ch7 0x0x0x_0000 pdma_isr8 pdma_ba_ch8+0x24 r/w pdma interrupt status register ch8 0x0x0x_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved blkd_if tabort_if bits descriptions [31:2] reserved reserved [1] blkd_if block transfer done interrupt flag this bit indicates that pdma has finished all transfer. 1 = done 0 = not finished yet software can write 1 to clear this bit to zero [0] tabort_if pdma read/write target abort interrupt flag 1 = bus error response received 0 = no bus error response received software can write 1 to clear this bit to zero note: the pdma_isr [tabort_if] indicate bus master receiv ed error response or not, if bus master received occur it means that target abort is happened. pdmac will stop transfer an d respond this event to software then go to idle state. when target abort occurred, software must reset pdma, and then transfer those data again. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 531 - revision v1.06 pdma shared buffer fifo 0 (pdma_sbuf0_cx) register offset r/w description reset value pdma_sbuf0_c0 pdma_ba_ch0+0x080 r pdma shared buffer fifo 0 register ch0 0x0000_0000 pdma_sbuf0_c1 pdma_ba_ch1+0x180 r pdma shared buffer fifo 0 register ch1 0x0000_0000 pdma_sbuf0_c2 pdma_ba_ch2+0x280 r pdma shared buffer fifo 0 register ch2 0x0000_0000 pdma_sbuf0_c3 pdma_ba_ch3+0x380 r pdma shared buffer fifo 0 register ch3 0x0000_0000 pdma_sbuf0_c4 pdma_ba_ch4+0x480 r pdma shared buffer fifo 0 register ch4 0x0000_0000 pdma_sbuf0_c5 pdma_ba_ch5+0x580 r pdma shared buffer fifo 0 register ch5 0x0000_0000 pdma_sbuf0_c6 pdma_ba_ch6+0x680 r pdma shared buffer fifo 0 register ch6 0x0000_0000 pdma_sbuf0_c7 pdma_ba_ch7+0x780 r pdma shared buffer fifo 0 register ch7 0x0000_0000 pdma_sbuf0_c8 pdma_ba_ch8+0x880 r pdma shared buffer fifo 0 register ch8 0x0000_0000 notice: low density only support pdma channel 0. 31 30 29 28 27 26 25 24 pdma_sbuf0 [31:24] 23 22 21 20 19 18 17 16 pdma_sbuf0 [23:16] 15 14 13 12 11 10 9 8 pdma_sbuf0 [15:8] 7 6 5 4 3 2 1 0 pdma_sbuf0 [7:0] bits descriptions [31:0] pdma_sbuf0 pdma shared buffer fifo 0 (read only) each channel has its own 1 words internal buffer. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 532 - revision v1.06 pdma global control and stat us register (pdma_gcrcsr) register offset r/w description reset value pdma_gcrcsr pdma_ba_gcr+0x00 r/w pdma global co ntrol and status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved clk8_en 15 14 13 12 11 10 9 8 clk7_en clk6_en clk5_en clk4_en clk3_en clk2_en clk1_en clk0_en 7 6 5 4 3 2 1 0 reserved bits descriptions [31:17] reserved reserved [16] clk8_en pdma controller channel 8 clock enable control (medium density only) 0 = disable 1 = enable [15] clk7_en pdma controller channel 7 clock enable control (medium density only) 0 = disable 1 = enable [14] clk6_en pdma controller channel 6 clock enable control (medium density only) 0 = disable 1 = enable [13] clk5_en pdma controller channel 5 clock enable control (medium density only) 0 = disable 1 = enable [12] clk4_en pdma controller channel 4 clock enable control (medium density only) 0 = disable 1 = enable [11 clk3_en pdma controller channel 3 clock enable control (medium density only) 0 = disable 1 = enable [10 clk2_en pdma controller channel 2 clock enable control (medium density only) 0 = disable 1 = enable numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 533 - revision v1.06 [9] clk1_en pdma controller channel 1 clock enable control (medium density only) 0 = disable 1 = enable [8] clk0_en pdma controller channel 0 clock enable control 0 = disable 1 = enable [7:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 534 - revision v1.06 pdma service selection control register 0 (pdssr0) register address r/w description reset value pdssr0 pdma_ba_gcr+0x04 r/w pdma service select ion control register 0 0xffff_ffff 31 30 29 28 27 26 25 24 spi3_txsel spi3_rxsel 23 22 21 20 19 18 17 16 spi2_txsel spi2_rxsel 15 14 13 12 11 10 9 8 spi1_txsel spi1_rxsel 7 6 5 4 3 2 1 0 spi0_txsel spi0_rxsel bits descriptions [31:28] spi3_txsel pdma spi3 tx selection (medium density only) this filed defines which pdma channel is connected to the on-chip peripheral spi3 tx. software can configure the tx channel setting by spi3_txsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [27:24] spi3_rxsel pdma spi3 rx selection (medium density only) this filed defines which pdma channel is connected to the on-chip peripheral spi3 rx. software can configure the rx channel setting by spi3_rxsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [23:20] spi2_txsel pdma spi2 tx selection (medium density only) this filed defines which pdma channel is connected to the on-chip peripheral spi2 tx. software can configure the tx channel setting by spi2_txsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [19:16] spi2_rxsel pdma spi2 rx selection (medium density only) this filed defines which pdma channel is connected to the on-chip peripheral spi2 rx. software can configure the rx channel setting by spi2_rxsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [15:12] spi1_txsel pdma spi1 tx selection this filed defines which pdma channel is connected to the on-chip peripheral spi1 tx. software can configure the tx channel setting by spi1_txsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [11:8] spi1_rxsel pdma spi1 rx selection this filed defines which pdma channel is connected to the on-chip peripheral spi1 rx. software can configure the rx channel setting by spi1_rxsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 535 - revision v1.06 [7:4] spi0_txsel pdma spi0 tx selection this filed defines which pdma channel is connected to the on-chip peripheral spi0 tx. software can configure the tx channel setting by spi0_txsel. the channel configuration is the same as spi0_rxsel fi eld. please refer to the explanation of spi0_rxsel. [3:0] spi0_rxsel pdma spi0 rx selection this filed defines which pdma channel is connected to the on-chip peripheral spi0 rx. software can change the channel rx setting by spi0_rxsel 4?b0000: ch0 4?b0001: ch1 4?b0010: ch2 4?b0011: ch3 4?b0100: ch4 4?b0101: ch5 4?b0110: ch6 4?b0111: ch7 4?b1000: ch8 others : reserved note: ex : spi0_rxsel = 4?b0110, that means spi0_rx is connected to pdma_ch6 (low density should set as 4?b0000 for pdma channel 0 only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 536 - revision v1.06 pdma service selection control register 1 (pdssr1) register address r/w description reset value pdssr1 pdma_ba_gcr+0x08 r/w pdma service select ion control register 1 0xffff_ffff 31 30 29 28 27 26 25 24 reserved adc_rxsel 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 uart1_txsel uart1_rxsel 7 6 5 4 3 2 1 0 uart0_txsel uart0_rxsel bits descriptions [31:28] reserved reserved [27:24] adc_rxsel pdma adc rx selection this filed defines which pdma channel is connected to the on-chip peripheral adc rx. software can configure the rx c hannel setting by adc_rxsel. the channel configuration is the same as uart0_rxsel fi eld. please refer to the explanation of uart0_rxsel [23:16] reserved reserved [15:12] uart1_txsel pdma uart1 tx selection this filed defines which pdma channel is connected to the on-chip peripheral uart1 tx. software can configure the tx channel setting by uart1_txsel. the channel configuration is the same as uart0_rxsel field. please refer to the explanation of uart0_rxsel [11:8] uart1_rxsel pdma uart1 rx selection this filed defines which pdma channel is connected to the on-chip peripheral uart1 rx. software can configure the rx channel setting by uart1_rxsel. the channel configuration is the same as uart0_rxsel field. please refer to the explanation of uart0_rxsel [7:4] uart0_txsel pdma uart0 tx selection this filed defines which pdma channel is connected to the on-chip peripheral uart0 tx. software can configure the tx channel setting by uart0_txsel. the channel configuration is the same as uart0_rxsel field. please refer to the explanation of uart0_rxsel numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 537 - revision v1.06 [3:0] uart0_rxsel this filed defines which pdma channel is connected to the on-chip peripheral uart0 rx. software can change the channel rx setting by uart0_rxsel 4?b0000: ch0 4?b0001: ch1 4?b0010: ch2 4?b0011: ch3 4?b0100: ch4 4?b0101: ch5 4?b0110: ch6 4?b0111: ch7 4?b1000: ch8 others : reserved note: ex : uart0_rxsel = 4?b0110, that means uart0_rx is connected to pdma_ch6 (low density should set as 4?b0000 for pdma channel 0 only) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 538 - revision v1.06 pdma global interrupt status register (pdma_gcrisr) register offset r/w description reset value pdma_gcrisr pdma_ba_gcr+0x0c r pdma global interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 intr reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved intr8 7 6 5 4 3 2 1 0 intr7 intr6 intr5 intr4 intr3 intr2 intr1 intr0 bits descriptions [31] intr interrupt pin status this bit is the interrupt pin status of pdma controller. note: this bit is read only [30:9] reserved reserved [8] intr8 interrupt pin status of channel 8 (medium density only) this bit is the interrupt pin status of pdma channel8. note: this bit is read only [7] intr7 interrupt pin status of channel 7 (medium density only) this bit is the interrupt pin status of pdma channel7. note: this bit is read only [6] intr6 interrupt pin status of channel 6 (medium density only) this bit is the interrupt pin status of pdma channel6. note: this bit is read only [5] intr5 interrupt pin status of channel 5 (medium density only) this bit is the interrupt pin status of pdma channel5. note: this bit is read only [4] intr4 interrupt pin status of channel 4 (medium density only) this bit is the interrupt pin status of pdma channel4. note: this bit is read only numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 539 - revision v1.06 [3] intr3 interrupt pin status of channel 3 (medium density only) this bit is the interrupt pin status of pdma channel3. note: this bit is read only [2] intr2 interrupt pin status of channel 2 (medium density only) this bit is the interrupt pin status of pdma channel2. note: this bit is read only [1] intr1 interrupt pin status of channel 1 (medium density only) this bit is the interrupt pin status of pdma channel1. note: this bit is read only [0] intr0 interrupt pin status of channel 0 this bit is the interrupt pin status of pdma channel0. note: this bit is read only numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 540 - revision v1.06 pdma service selection control register 2 (pdssr2) register offset r/w description reset value pdssr2 pdma_ba_gcr+0x10 r/w pdma service sele ction control register 2 0x0000_00ff 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 i2s_txsel i2s_rxsel bits descriptions [31:8] reserved reserved [7:4] i2s_txsel pdma i 2 s tx selection this filed defines which pdma channel is connected to the on-chip peripheral i 2 s tx. software can configure the tx channel setting by i2s_txsel. the channel configuration is the same as i2s_rxsel field. please refer to the explanation of i2s_rxsel. [3:0] i2s_rxsel pdma i 2 s rx selection this filed defines which pdma channel is connected to the on-chip peripheral i 2 s rx. software can change the channel rx setting by i2s_rxsel 4?b0000: ch0 4?b0001: ch1 4?b0010: ch2 4?b0011: ch3 4?b0100: ch4 4?b0101: ch5 4?b0110: ch6 4?b0111: ch7 4?b1000: ch8 others : reserved note: ex : i2s_rxsel = 4?b0110, that means i2s_rx is connected to pdma_ch6 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 541 - revision v1.06 5.19 external bus interface (ebi) 5.19.1 overview the numicro ? nuc100 low density lqfp-64 package equips an external bus interface (ebi) for external device used. to save the connections between external device and this chip, ebi support address bus and data bus multiplex mode. and, address latch en able (ale) signal supported differentiate the address and data cycle. 5.19.2 features external bus interface has the following functions: z external devices with max. 64k-byte size (8 bit data width)/128k-byte (16 bit data width) supported z variable external bus base clock (mclk) supported z 8 bit or 16 bit data width supported z variable data access time (tacc), address latch enable time (tale) and address hold time (tahd) supported z address bus and data bus multiplex mode supported to save the address pins z configurable idle cycle supported for different access condition: write command finish (w2x), read-to-read (r2r) numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 542 - revision v1.06 5.19.3 block diagram ahb bus figure 5-108 ebi block diagram 5.19.4 function description 5.19.4.1 ebi area and address hit ebi mapping address is lo cated at 0x6000_0000 ~ 0x6001_ffff and the total memory space is 128kbyte. when system request address hit ebi?s memory space, the corresponding ebi chip select signal is assert and ebi state machine operates. for an 8-bit device (64kbyte), ebi mapped th is 64kbyte device to 0x6000_0000 ~ 0x6000_ffff and 0x6001_0000 ~ 0x6001_ffff simultaneously. 5.19.4.2 ebi data width connection ebi suppo rt device whose address bus and data bus are multiplexed. for the external device with separated address and data bus, the connection to device needs additional logic to latch the address. in this case, pin ale is connected to the latch device to latch the address value. pin ad is the input of the latch device, and the output of the latch device is connected to the address of external device. for 16-bit device, the ad [15: 0] shared by address and 16-bit data. for 8-bit device, only ad [7:0] shared by address and 8- bit data, ad [15:8] is dedicated for address and could be connected to 8-bit device directly. for 8-bit data width, chip system address bit [15: 0] is used as the device?s address [15:0]. for 16- numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 543 - revision v1.06 bit data width, chip system address bit [16:1] is used as the device?s address [15:0] and chip system address bit [0] is useless. ebi bit width system address (ahbadr) ebi address (ad) 8 bit ahbadr[15:0] ad[15:0] 16 bit ahbadr[16:1] ad[15:0] figure 5-109 connection of 16-bit ebi data width with 16-bit device figure 5-110 connection of 8-bit ebi data width with 8-bit device when system access data width is lager than ebi data width, ebi controller will finish a system access command by operating ebi access more than once. for example, if system requests a 32-bit data through ebi device, ebi controller will operate accessing four times when setting ebi data width with 8-bit. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 544 - revision v1.06 5.19.4.3 ebi operating control mclk control in the chip, all ebi signals will be synchronized by mclk when ebi is operating. when chip connects to the external device with slower operating frequency, the mclk can divide most to hclk/32 by setting mclkdiv of register ebicon. therefore, chip can suitable for a wide frequency range of ebi device. if mclk is set to hclk/1, ebi signals are synchronized by positive edge of mclk, else by negative edge of mclk. operation and access timing control in the start of access, chip select (ncs) asse rts to low and wait one mclk for address setup time (tasu) for address stable. then ale asserts to hi gh after address is stable and keeps for a period of time (tale) for address latch. after latch address, ale asserts to low and wait one mclk for latch hold time (tlhd) and another one mclk cy cle (ta2d) that is inserted behind address hold time to be the bus turn-around time for address change to data. then nrd asserts to low when read access or nwr asserts to low when write access. then nrd or nwr asserts to high after keeps access time (tacc) for reading output stable or writing finish. after that, ebi signals keep for data access hold time (tahd) and chip select asserts to high, address is released by current access control. ebi controller provides a flexible timing control fo r different external device. in ebi timing control, tasu, tlhd and ta2d are fixed to 1 mclk cycle, tahd can modulate to 1~8 mclk cycles by setting exttahd of register extime, tacc can modulate to 1~32 mclk cycles by setting exttacc of register extime, and tale can modulat e to 1~8 mclk cycles by setting tale of register ebicon. parameter value unit description tasu 1 mclk address latch setup time. tale 1 ~ 8 mclk ale high period. controlled by exttale of ebicon. tlhd 1 mclk address latch hold time. ta2d 1 mclk address to data delay (bus turn-around time). tacc 1 ~ 32 mclk data access time. controlled by exttacc of extime. tahd 1 ~ 8 mclk data access hold time. controlled by exttahb of extime. idle 0 ~ 15 mclk idle cycle. controlled by extir2r and extiw2x of extime. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 545 - revision v1.06 ncs ad[15:0] mclk nrd tacc tasu tahd nwr ad[15:0] ale tale tlhd ta2d address output[15:0] wdata output[15:0] rdata input address output[15:0] figure 5-111 timing control waveform for 16bit data width figure 5-111 is an example of setting 16bit data width. in this example, ad bu s is used for being address[15:0] and data[15:0]. when ale assert to high, ad is address output. after address is latched, ale asserts to low and the ad bus change to high impedance to wait device output data in read access operation, or it is used for being write data output. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 546 - revision v1.06 ncs ad[7:0] mclk nrd tacc tasu tahd nwr ad[7:0] ale tale tlhd ta2d address output[7:0] wdata output[7:0] rdata input address output[7:0] ad[15:8] address output[15:8] ad[15:8] address output[15:8] figure 5-112 timing control waveform for 8bit data width figure 5-112 is an example of setting 8bit data wi dth . the difference between 8bit and 16bit data width is ad[15:8]. in 8bit data width setting, ad[15:8] always be address[15:8] output so that external latch need only 8 bit width. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 547 - revision v1.06 insert idle cycle when ebi accessing continuously, there may occur bus conflict if the device access time is much slow with system operating. ebi controller supply additional idle cycle to solve this problem. during idle cycle, all control signals of ebi are inactive. figure 5-113 show idle cycle as below: figure 5-113 timing control waveform for insert idle cycle there are two conditions that ebi can insert idle cycle by timing control: 1. after write access 2. after read access and before next read access by setting extiw2x, and extir2r of register extime, the time of idle cycle can be specified from 0~15 mclk. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 548 - revision v1.06 5.19.5 register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value ebi_ba = 0x5001_0000 ebicon ebi_ba+0x00 r/w external bus interfac e general control register 0x0000_0000 extime ebi_ba+0x04 r/w external bus interf ace timing control register 0x0000_0000 5.19.6 register description external bus interface control register (ebicon) register offset r/w description reset value ebicon ebi_ba+0x00 r/w external bus interfac e general control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reversed exttale 15 14 13 12 11 10 9 8 reversed mclkdiv 7 6 5 4 3 2 1 0 reversed extbw16 exten bits descriptions [31:19] reserved reserved [18:16] exttale expand time of ale the ale width (tale) to latch the address can be controlled by exttale. tale = (exttale+1)*mclk [15:11] reserved reserved [10:8] mclkdiv external output clock divider the frequency of ebi output clock is cont rolled by mclkdiv as follows table: mclkdiv output clock (mclk) 000 hclk/1 001 hclk/2 010 hclk/4 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 549 - revision v1.06 011 hclk/8 100 hclk/16 101 hclk/32 11x default notice: default value of output clock is hclk/1 [7:2] reserved reserved [1] extbw16 ebi data width 16 bit this bit defines if the dat a bus is 8-bit or 16-bit. 1 = ebi data width is 16 bit 0 = ebi data width is 8 bit [0] exten ebi enable this bit is the func tional enable bit for ebi. 1 = ebi function is enabled 0 = ebi function is disabled numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 550 - revision v1.06 external bus interface timing control register (extime) register offset r/w description reset value extime ebi_ba+0x04 r/w external bus interf ace timing control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved extir2r 23 22 21 20 19 18 17 16 reversed 15 14 13 12 11 10 9 8 extiw2x reversed exttahd 7 6 5 4 3 2 1 0 exttacc reversed bits descriptions [31:28] reserved reserved [27:24] extir2r idle state cycle between read-read when read action is finish and next action is going to read, idle state is inserted and ncs return to high if extir2r is not zero. idle state cycle = (extir2r*mclk) [23:16] reserved reserved [15:12] extiw2x idle state cycle after write when write action is finish, idle state is in serted and ncs return to high if extiw2x is not zero. idle state cycle = (extiw2x*mclk) [11] reserved reserved [10:8] exttahd ebi data access hold time exttahd define data access hold time (tahd). tahd = (exttahd +1) * mclk [7:3] exttacc ebi data access time exttacc define data access time (tacc). tacc = (exttacc +1) * mclk [2:0] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 551 - revision v1.06 6 flash memory controller (fmc) 6.1 overview numicro ? nuc100 series equips with 128/64/32k bytes on chip embedded flash eprom for application program memory (aprom) that c an be updated through isp procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on, cortex-m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro ? nuc100 series also provides additional data flash for user, to store some applicatio n dependent data before ch ip power off. for 128k bytes aprom device, the data flash is shared with original 128k program memory and its start address is configurable and defined by user applic ation request in config1. for 64k/32k bytes aprom device, the data flash is fixed at 4k. 6.2 features z run up to 50 mhz with zero wait state for continuous address read access z 128/64/32kb application program memory (aprom) (low density only support up to 64kb size) z 4kb in system programming (isp) loader program memory (ldrom) z configurable or fixed 4kb data flash with 512 bytes page erase unit z programmable data flash star t address for 128k aprom device z in system program (isp) to update on chip flash eprom numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 552 - revision v1.06 6.3 block diagram the flash memory controller consist of ahb slave interface, isp control logic, writer interface and flash macro interface timing control logic. the block diagram of flash memory controller is shown as following: 32kb 64kb 128kb serial wire debug interface figure 6-1 medium density flash memory control block diagram numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 553 - revision v1.06 32kb 64kb serial wire debug interface figure 6-2 low density flash memory control block diagram numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 554 - revision v1.06 6.4 flash memory organization numicro ? nuc100 series flash memory consists of program memory (128/64/32kb), data flash, isp loader program memory, user configuration. us er configuration block provides several bytes to control system logic, like flash security lock, boot select, brown out voltage level, data flash base address, ..., and so on. it wo rks like a fuse for power on setting. it is loaded from flash memory to its corresponding control registers du ring chip power on. user can set these bits according to application request by writer before chip is mounted on pcb. the data flash start address and its size can defined by user depends on application in 128kb aprom device. for 64/32kb aprom devices, its size is 4kb and start address is fixed at 0x0001_f000. block name size start address end address ap-rom 32/64/(128-0.5*n) kb 0x0000_0000 0x0000_7fff (32kb) 0x0000_ffff (64kb) dfbadr-1 (128kb if dfen=0) reserved for future use 896 kb 0x0002_0000 0x000f_ffff data flash 4/4/0.5*n kb 0x0001_f000 dfbadr 0x0001_ffff ld-rom 4 kb 0x0010 _0000 0x0010_0fff user configuration 2 words 0x0030_0000 0x0030_0004 table 6-1 medium density memory address map block name size start address end address ap-rom 32/64kb 0x0000_0000 0x0000_7fff (32kb) 0x0000_ffff (64kb) reserved for future use 960 kb 0x0001_0000 0x000f_ffff data flash 4 kb 0x00 01_f000 0x0001_ffff ld-rom 4 kb 0x0010 _0000 0x0010_0fff user configuration 1 words 0x0030_0000 0x0030_0000 table 6-2 low density memory address map numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 555 - revision v1.06 the flash memory organization is shown as below: figure 6-3 low density flash memory organization numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 556 - revision v1.06 user configuration application program memory isp loader program memory 0x0000_0000 0x0010_0000 reserved for further used 0x0001_ffff 0x0030_0000 0x0030_03ff config0 0x0030_0000 0x0010_0fff 1mb data flash reserved for further used 0x0001_f000 0x0000_ffff figure 6-4 low density flash memory organization numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 557 - revision v1.06 6.5 boot selection numicro ? nuc100 series provides in system pr ogramming (isp) feature to enable user to update program memory when chip is mounted on pcb. a dedicated 4kb program memory is used to store isp firmware. users can select to start program fetch from aprom or ldrom by (cbs) in config0. 6.6 data flash numicro ? nuc100 series provides data flash for user to store data. it is read/write through isp procedure. the size of each erase unit is 512 bytes. when a word will be changed, all 128 words need to be copied to another page or sram in advance. for 128kb aprom device, the data flash and application program share the same 128 kb memory, if dfen bit in config0 is enabled, the data flash base address is defined by dfba dr and application program memory size is (128- 0.5*n)kb and data flash size is 0.5*n kb. for 64/32kb aprom devices, data flash size is 4kb and start address is fixed at 0x0001_f000. figure 6-5 medium density flash memory structure numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 558 - revision v1.06 figure 6-6 low density flash memory structure numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 559 - revision v1.06 6.7 user configuration config0 (address = 0x0030_0000) 31 30 29 28 27 26 25 24 reserved ckf reserved cfosc 23 22 21 20 19 18 17 16 cboden cbov1 cbov0 cborst reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 cbs reserved lock dfen bits descriptions [31:29] reserved reserved [28] ckf xt1 clock filter enable 0 = disable xt1 clock filter 1 = enable xt1 clock filter [27] reserved reserved [26:24] cfosc cpu clock source selection after reset fosc[2:0] clock source 000 external 4~24 mhz crystal clock 111 internal rc 22.1184 mhz oscillator clock others reserved the value of cfosc will be load to clksel0.hclk_s[2:0] in system register after any reset occurs. [23] cboden brown out detector enable 0= enable brown out detect after power on 1= disable brown out detect after power on [22:21] cbov1-0 brown out voltage selection cbov1 cbov0 brown out voltage 1 1 4.5v 1 0 3.8v 0 1 2.7v 0 0 2.2v numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 560 - revision v1.06 [20] cborst brown out reset enable 0 = enable brown out reset after power on 1 = disable brown out reset after power on [19:8] reserved reserved [7] cbs chip boot selection 0 = chip boot from ldrom 1 = chip boot from aprom [6:2] reserved reserved [1] lock security lock 0 = flash data is locked 1 = flash data is not locked when flash data is locked, only device id, config0 and config1 can be read by writer and icp through serial debug interface. othe rs data is locked as 0xffffffff. isp can read data anywhere regardless of lock bit value. [0] dfen data flash enable (this bit is work only for 128kb aprom device) 0 = enable data flash 1 = disable data flash numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 561 - revision v1.06 config1 (address = 0x0030_0004) 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved dfbadr.19 dfbadr.18 dfbadr.17 dfbadr.16 15 14 13 12 11 10 9 8 dfbadr.15 dfbadr.14 dfbadr.13 dfbadr.12 dfbadr.11 dfbadr.10 dfbadr.9 dfbadr.8 7 6 5 4 3 2 1 0 dfbadr.7 dfbadr.6 dfbadr.5 dfbadr.4 dfbadr.3 dfbadr.2 dfbadr.1 dfbadr.0 bits descriptions [31:20] reserved reserved (it is mandatory to progr am 0x00 to these reserved bits) [19:0] dfbadr data flash base address (this register is work only for 128kb aprom device) for 128kb aprom device, its data flash base address is defined by user. since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0. this configuration is only valid for 128kb flash device. numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 562 - revision v1.06 6.8 in system program (isp) the program memory and data flash supports both in hardware programming and in system programming (isp). hardware programming mo de uses gang-writers to reduce programming costs and time to market while the products enter into the mass production state. however, if the product is just under development or the end produ ct needs firmware updating in the hand of an end user, the hardware programming mode will make repeated programming difficult and inconvenient. isp method makes it easy and possible. numicro ? nuc100 series supports isp mode allowing a device to be reprogrammed under software control. furthermore, the capability to update the application firmware makes wide range of applications possible. isp is performed without removing the microcontroll er from the system. various interfaces enable ldrom firmware to get new program code easily. the most common method to perform isp is via uart along with the firmware in ldrom. general speaking, pc transfers the new aprom code through serial port. then ldrom firmware receives it and re-programs into aprom through isp commands. nuvoton provides isp firmware and pc application program for numicro ? nuc100 series. it makes users quite easy perform isp through nuvoton isp tool. 6.8.1 isp procedure numicro ? nuc100 series supports booting from aprom or ldrom initially defined by user configuration bit (cbs). if user wants to updat e application program in aprom, he can write bs=1 and starts software reset to make chip boot from ldrom. the first step to start isp function is write ispen bit to 1. s/w is required to write regwrprot regi ster in global control register (gcr, 0x5000_0100) with 0x59, 0x16 and 0x88 before writing ispcon register. this procedure is used to protect flash memory fr om destroying owning to unintended write during power on/off duration. several error conditions are checked after softw are writes ispgo bit. if error condition occurs, isp operation is not been started and isp fail flag will be set instead of. ispff flag is cleared by s/w, it will not be over written in next isp operation. the next isp procedure can be started even ispff bit keeps at 1. it is recommended that s/ w to check ispff bit and clear it after each isp operation if it is set to 1. when ispgo bit is set, cpu will wait for isp operation finish, during this period; peripheral still keeps working as usual. if any interrupt request oc cur, cpu will not service it till isp operation finish. when isp operation is finished, the isp go bit will be cleared by hardware automatically. user can know if isp operation is finished by ch ecking this bit. user should add isb instruction next to the instruction which set 1 to ispgo bit to ensure correct execution of the instructions following isp operation. cpu writes ispgo bit isp operation hclk hready cpu is halted but other peripherials keep working ss ss note that numicro ? nuc100 series allows user to update config value by isp. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 563 - revision v1.06 power on cbs = 1 ? fetch code from ap-rom fetch code from ld-rom execute isp? enable ispen set ispgo = 1 end of isp operation ? (read ispdat) & check ispff = 1? yes yes no update ld-rom or write dataflash end of flash operation a clear bs to 0 and set swrst = 1 c clear ispen and and back to main program no write ispadr/ ispcmd/ ispdat ? add isb instruction check ispgo = 0 ? b c b b a a no yes numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 564 - revision v1.06 ispcmd ispadr ispdat isp mode foen fcen fctrl[3:0] a21 a20 a[19:0] d[31:0] flash page erase 1 0 0010 0 a20 address in a[19:0] x flash program 1 0 0001 0 a20 address in a[19:0] data in d[31:0] flash read 0 0 0000 0 a20 address in a[19:0] data out d[31:0] config page erase 1 0 0010 1 1 address in a[19:0] x config program 1 0 0001 1 1 address in a[19:0] data in d[31:0] config read 0 0 0000 1 1 address in a[19:0] data out d[31:0] table 6-3 isp mode numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 565 - revision v1.06 6.9 flash control register map r : read only, w : write only, r/w : both read and write register offset r/w description reset value base address (fmc_ba) : 0x5000_c000 ispcon fmc_ba+0x000 r/w isp control register 0x0000_0000 ispadr fmc_ba+0x004 r/w isp address register 0x0000_0000 ispdat fmc_ba+0x008 r/w isp data register 0x0000_0000 ispcmd fmc_ba+0x00c r/w isp command register 0x0000_0000 isptrg fmc_ba+0x010 r/w isp trigger register 0x0000_0000 dfbadr fmc_ba+0x014 r data flash start address ( ap rom size is less than 128kb) 0x0001_f000 dfbadr fmc_ba+0x014 r data flash start address (ap rom size is equal to 128kb) 0x0000_0000 fatcon fmc_ba+0x018 r/w flash access window control register 0x0000_0000 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 566 - revision v1.06 6.10 flash control register description isp control register (ispcon) register offset r/w description reset value ispcon fmc_ba+0x00 r/w isp control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved et reserved pt 7 6 5 4 3 2 1 0 reserved ispff lduen cfguen reserved bs ispen bits descriptions [31:15] reserved reserved [14:12] et[2:0] flash erase time (write-protection bits) et[2] et[1] et[0] erase time (ms) 0 0 0 20 (default) 0 0 1 25 0 1 0 30 0 1 1 35 1 0 0 3 1 0 1 5 1 1 0 10 1 1 1 15 [11] reserved reserved numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 567 - revision v1.06 [8:10] pt[2:0] flash program time (write-protection bits) pt[2] pt[1] pt[0] program time (us) 0 0 0 40 0 0 1 45 0 1 0 50 0 1 1 55 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 [7] reserved reserved [6] ispff isp fail flag (write-protection bit) this bit is set by hardware when a trigger ed isp meets any of the following conditions: (1) aprom writes to itself (2) ldrom writes to itself (3) config is erased/programmed if cfguen is set to 0 (4) destination address is illegal , such as over an available range write 1 to clear. [5] lduen ldrom update enable (write-protection bit) ldrom update enable bit. 1 = ldrom can be updated when the chip runs in aprom 0 = ldrom can not be updated [4] cfguen enable config-bits update by isp (write-protection bit) 1 = enable isp can update config-bits 0 = disable isp can update config-bits [3:2] reserved reserved [1] bs boot select (write-protection bit) set/clear this bit to select next booti ng from ldrom/aprom, respectively. this bit also functions as chip booting status flag, which can be used to check where chip booted from. this bit is initiated with the inversed value of cbs in config0 after power- on reset; it keeps the same value at other reset. 1 = boot from ldrom 0 = boot from aprom [0] ispen isp enable (write-protection bit) isp function enable bit. set this bit to enable isp function. 1 = enable isp function 0 = disable isp function numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 568 - revision v1.06 isp address (ispadr) register offset r/w description reset value ispadr fmc_ba+ 0x04 r/w isp address register 0x0000_0000 31 30 29 28 27 26 25 24 ispadr[31:24] 23 22 21 20 19 18 17 16 ispadr[23:16] 15 14 13 12 11 10 9 8 ispadr[15:8] 7 6 5 4 3 2 1 0 ispadr[7:0] bits descriptions [31:0] ispadr isp address numicro ? nuc100 series equips with a maximum 32kx32 embedded flash, it supports word program only. ispadr[1:0] must be kept 00b for isp operation. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 569 - revision v1.06 isp data register (ispdat) register offset r/w description reset value ispdat fmc_ba+ 0x08 r/w isp data register 0x0000_0000 31 30 29 28 27 26 25 24 ispdat[31:24] 23 22 21 20 19 18 17 16 ispdat [23:16] 15 14 13 12 11 10 9 8 ispdat [15:8] 7 6 5 4 3 2 1 0 ispdat [7:0] bits descriptions [31:0] ispdat isp data write data to this register before isp program operation read data from this register after isp read operation numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 570 - revision v1.06 isp command (ispcmd) register offset r/w description reset value ispcmd fmc_ba+ 0x0c r/w isp command register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved foen fcen fctrl bits descriptions [31:6] reserved reserved [5] foen [4] fcen [3:0] fctrl isp command isp command table is showed below: operation mode foen fcen fctrl[3:0] read 0 0 0 0 0 0 program 1 0 0 0 0 1 page erase 1 0 0 0 1 0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 571 - revision v1.06 isp trigger control register (isptrg) register offset r/w description reset value isptrg fmc_ba+ 0x10 r/w isp trigger control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ispgo bits descriptions [31:1] reserved reserved [0] ispgo isp start trigger write 1 to start isp operation and this bit will be cleared to 0 by hardware automatically when isp operation is finished. 1 = isp is on going 0 = isp operation is finished numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 572 - revision v1.06 data flash base address register (dfbadr) register offset r/w description reset value dfbadr fmc_ba+ 0x14 r data flash base address 0x0001_f000 31 30 29 28 27 26 25 24 dfbadr[31:23] 23 22 21 20 19 18 17 16 dfbadr[23:16] 15 14 13 12 11 10 9 8 dfbadr[15:8] 7 6 5 4 3 2 1 0 dfbadr[7:0] bits descriptions [31:0] dfbadr data flash base address this register indicates data flash st art address. it is a read only register. for 128kb flash memory device, the data flash size is defined by user configuration, register content is loaded from config1 when chip power on but for 64/32kb device, it is fixed at 0x0001_f000. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 573 - revision v1.06 flash access time control register (fatcon) register offset r/w description reset value fatcon fmc_ba + 0x18 r/w flash access time control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved fats[2:0] fpsen bits descriptions [31:4] reserved reserved [3:1] fats flash access time window select (write-protection bits) these bits are used to decide flash sense amplifier active duration. fats access time window (ns) 000 40 001 50 010 60 011 70 100 80 101 90 110 100 111 reserved [0] fpsen flash power save enable (write-protection bit) if cpu clock is slower than 24 mhz, then s/w can enable flash power saving function. 1 = enable flash power saving 0 = disable flash power saving numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 574 - revision v1.06 7 electrical characteristics 7.1 absolute maximum ratings symbol parameter min max unit dc power supply vdd ? vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into vdd - 120 ma maximum current out of vss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions bey ond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 575 - revision v1.06 7.2 dc electrical characteristics 7.2.1 numicro ? nuc10 0/nuc120/nuc130/nuc140 me dium density dc electrical characteristics (vdd-vss=3.3v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5v ~ 5.5v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 54 ma v dd = 5.5v@50mhz, enable all ip and pll, xtal=12mhz i dd2 31 ma v dd = 5.5v@50mhz, disable all ip and enable pll, xtal=12mhz i dd3 51 ma v dd = 3v@50mhz, enable all ip and pll, xtal=12mhz operating current normal run mode @ 50mhz i dd4 28 ma v dd = 3v@50mhz, disable all ip and enable pll, xtal=12mhz i dd5 22 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz i dd6 14 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xtal=12mhz operating current normal run mode @ 12mhz i dd7 20 ma v dd = 3v@12mhz, enable all ip and disable pll, xtal=12mhz numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 576 - revision v1.06 specification parameter sym. min. typ. max. unit test conditions i dd8 12 ma v dd = 3v@12mhz, disable all ip and disable pll, xtal=12mhz i dd9 15 ma v dd = 5v@4mhz, enable all ip and disable pll, xtal=4mhz i dd10 11 ma v dd = 5v@4mhz, disable all ip and disable pll, xtal=4mhz i dd11 13 ma v dd = 3v@4mhz, enable all ip and disable pll, xtal=4mhz operating current normal run mode @ 4mhz i dd12 9 ma v dd = 3v@4mhz, disable all ip and disable pll, xtal=4mhz i idle1 38 ma v dd = 5.5v@50mhz, enable all ip and pll, xtal=12mhz i idle2 15 ma v dd =5.5v@50mhz, disable all ip and enable pll, xtal=12mhz i idle3 35 ma v dd = 3v@50mhz, enable all ip and pll, xtal=12mhz operating current idle mode @ 50mhz i idle4 13 ma v dd = 3v@50mhz, disable all ip and enable pll, xtal=12mhz i idle5 13 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz i idle6 5.5 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xtal=12mhz i idle7 12 ma v dd = 3v@12mhz, enable all ip and disable pll, xtal=12mhz operating current idle mode @ 12mhz i idle8 4 ma v dd = 3v@12mhz, disable all ip and disable pll, xtal=12mhz numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 577 - revision v1.06 specification parameter sym. min. typ. max. unit test conditions i idle9 8.5 ma v dd = 5v@4mhz, enable all ip and disable pll, xtal=4mhz i idle10 3.5 ma v dd = 5v@4mhz, disable all ip and disable pll, xtal=4mhz i idle11 7 ma v dd = 3v@4mhz, enable all ip and disable pll, xtal=4mhz operating current idle mode @ 4mhz i idle12 2.5 ma v dd = 3v@4mhz, disable all ip and disable pll, xtal=4mhz i pwd1 23 a v dd = 5.5v, rtc off, no load @ disable bov function i pwd2 18 a v dd = 3.3v, rtc off, no load @ disable bov function i pwd3 28 a v dd = 5.5v, rtc run , no load @ disable bov function standby current power-down mode (deep sleep mode) i pwd4 22 a v dd = 3.3v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5v, v in = 0v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5v, 0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 579 - revision v1.06 7.2.2 numicro ? nuc1 00/nuc120/nuc130/nuc140 low density dc electrical characteristics (vdd-vss=3.3v, ta = 25 c, fosc = 50 mhz unless otherwise specified.) specification parameter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v v dd =2.5v ~ 5.5v up to 50 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v v dd > 2.7v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 46 ma v dd = 5.5v@50mhz, enable all ip and pll, xtal=12mhz i dd2 30 ma v dd = 5.5v@50mhz, disable all ip and enable pll, xtal=12mhz i dd3 44 ma v dd = 3v@50mhz, enable all ip and pll, xtal=12mhz operating current normal run mode @ 50mhz i dd4 28 ma v dd = 3v@50mhz, disable all ip and enable pll, xtal=12mhz i dd5 19 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz i dd6 13 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xtal=12mhz i dd7 17 ma v dd = 3v@12mhz, enable all ip and disable pll, xtal=12mhz operating current normal run mode @ 12mhz i dd8 11.5 ma v dd = 3v@12mhz, disable all ip and disable pll, xtal=12mhz numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 580 - revision v1.06 specification parameter sym. min. typ. max. unit test conditions i dd9 13.5 ma v dd = 5v@4mhz, enable all ip and disable pll, xtal=4mhz i dd10 10 ma v dd = 5v@4mhz, disable all ip and disable pll, xtal=4mhz i dd11 12 ma v dd = 3v@4mhz, enable all ip and disable pll, xtal=4mhz operating current normal run mode @ 4mhz i dd12 8 ma v dd = 3v@4mhz, disable all ip and disable pll, xtal=4mhz i idle1 30 ma v dd = 5.5v@50mhz, enable all ip and pll, xtal=12mhz i idle2 13 ma v dd =5.5v@50mhz, disable all ip and enable pll, xtal=12mhz i idle3 28 ma v dd = 3v@50mhz, enable all ip and pll, xtal=12mhz operating current idle mode @ 50mhz i idle4 12 ma v dd = 3v@50mhz, disable all ip and enable pll, xtal=12mhz i idle5 11 ma v dd = 5.5v@12mhz, enable all ip and disable pll, xtal=12mhz i idle6 5 ma v dd = 5.5v@12mhz, disable all ip and disable pll, xtal=12mhz i idle7 10 ma v dd = 3v@12mhz, enable all ip and disable pll, xtal=12mhz operating current idle mode @ 12mhz i idle8 4 ma v dd = 3v@12mhz, disable all ip and disable pll, xtal=12mhz operating current idle mode i idle9 7 ma v dd = 5v@4mhz, enable all ip and disable pll, xtal=4mhz numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 581 - revision v1.06 specification parameter sym. min. typ. max. unit test conditions i idle10 3.5 ma v dd = 5v@4mhz, disable all ip and disable pll, xtal=4mhz i idle11 6 ma v dd = 3v@4mhz, enable all ip and disable pll, xtal=4mhz @ 4mhz i idle12 2.5 ma v dd = 3v@4mhz, disable all ip and disable pll, xtal=4mhz i pwd1 17 a v dd = 5.5v, rtc off, no load @ disable bov function i pwd2 14.5 a v dd = 3.3v, rtc off, no load @ disable bov function i pwd3 20 a v dd = 5.5v, rtc run , no load @ disable bov function standby current power-down mode (deep sleep mode) i pwd4 17 a v dd = 3.3v, rtc run , no load @ disable bov function input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5v, v in = 0v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a v dd = 5.5v, 0 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 583 - revision v1.06 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 584 - revision v1.06 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 585 - revision v1.06 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 586 - revision v1.06 7.2.4 idle current curve 1. xtal clock = 12 mhz, pll disable, all-ip disable unit: ma 2. xtal clock = 12 mhz, pll disable, all-ip enable unit: ma numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 587 - revision v1.06 3. xtal clock = 12 mhz, pll enable, all-ip disable unit: ma 4. xtal clock = 12 mhz, pll enable, all-ip enable unit: ma numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 588 - revision v1.06 7.2.5 power down current curve xtal clock = 12 mhz, pll disable unit: ma numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 589 - revision v1.06 7.3 ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 7.3.1 external 4~24mhz crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 vdd - 2.5 5 5.5 v 7.3.1.1 typical crystal application circuits crystal c1 c2 r 4mhz ~ 24 mhz without without without figure 7-1 typical crystal application circuit numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 590 - revision v1.06 7.3.2 external 32.768 khz crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32.768 - khz temperature - -40 - 85 vdd - 2.5 - 5.5 v 7.3.3 internal 22.1184 mhz oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 22.1184 - mhz +25 c; v dd =5v -1 - +1 % calibrated internal oscillator frequency -40 c~+85 c; vdd=2.5v~5.5v -3 - +3 % operation current v dd =5v - 500 - ua 7.3.4 internal 10 khz oscillator parameter condition min. typ. max. unit supply voltage [1] - 2.5 - 5.5 v center frequency - - 10 - khz +25 c; v dd =5v -30 - +30 % calibrated internal oscillator frequency -40 c~+85 c; v dd =2.5v~5.5v -50 - +50 % note: internal operation voltage comes from ldo. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 591 - revision v1.06 7.4 analog characteristics 7.4.1 specification of 12-bit saradc symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinea rity error - 3 - lsb inl integral nonlinearity error - 4 - lsb eo offset error - 1 10 lsb eg gain error (transfer gain) - 1 1.005 - - monotonic guaranteed fadc adc clock frequency - - 20 mhz tcal calibration time - 127 - clock ts sample time - 7 - clock tadc conversion time - 13 - clock fs sample rate - - 600 k sps vldo - 2.5 - v vadd supply voltage 3 - 5.5 v idd - 0.5 - ma idda supply current (avg.) - 1.5 - ma vref reference voltage - vdda - v irefp reference current (avg.) - 1 - ma vin reference voltage 0 - vref v cin capacitance - 5 - pf numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 592 - revision v1.06 7.4.2 specification of ldo & power management parameter min. typ. max. unit note input voltage 2.7 5 5.5 v v dd input voltage output voltage -10% 2.5 +10% v v dd > 2.7v temperature -40 25 85 quiescent current (pd=0) - 100 - ua quiescent current (pd=1) - 5 - ua iload (pd=0) - - 100 ma iload (pd=1) - - 100 ua cbp - 1 - uf resr=1ohm cload - 250 - pf note: 1. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between vdd and the closest vss pin of the device. 2. for ensuring power stability, a 4.7uf or higher capacitor must be connected between ldo pin and the closest vss pin of the device. also a 100nf bypass capacitor between ldo and vss help suppressing output noise. numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 593 - revision v1.06 7.4.3 specification of low voltage reset parameter condition min. typ. max. unit operation voltage - 1.7 - 5.5 v quiescent current vdd5v=5.5v - - 5 ua temperature - -40 25 85 temperature=25 1.7 2.0 2.3 v temperature=-40 - 2.4 - v threshold voltage temperature=85 - 1.6 - v hysteresis - 0 0 0 v 7.4.4 specification of brownout detector parameter condition min. typ. max. unit operation voltage - 2.5 - 5.5 v quiescent current avdd=5.5v - - 125 a temperature - -40 25 85 bov_vl[1:0]=11 4.4 4.5 4.6 v bov_vl [1:0]=10 3.7 3.8 3.9 v bov_vl [1:0]=01 2.6 2.7 2.8 v brown-out voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30 - 150 mv 7.4.5 specification of power-on reset (5v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na 7.4.6 specification of temperature sensor parameter conditions min. typ. max. unit numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 594 - revision v1.06 supply voltage [1] 2.5 - 5.5 v temperature -40 - 125 current consumption 6.4 - 10.5 ua gain -1.95 -2 -2.05 mv/ offset temp=0 688 708 730 mv note: internal operation voltage comes form ldo. 7.4.7 specification of comparator parameter condition min. typ. max. unit temperature - -40 25 85 vdd - 2.4 3 5.5 v vdd current 20ua@vdd=3v - 20 40 ua input offset voltage - - 5 15 mv output swing - 0.1 - vdd-0.1 v input common mode range - 0.1 - vdd-1.2 v dc gain - - 70 - db propagation delay @vcm=1.2v & vdiff=0.1v - 200 - ns comparison voltage 20mv@vcm=1v 50mv@vcm=0.1v 50mv@vcm=vdd-1.2 @10mv for non- hysteresis 10 20 - mv hysteresis one bit control w/o & w. hysteresis @vcm=0.4v ~ vdd-1.2v - 10 - mv wake up time @cinp=1.3v cinn=1.2v - - 2 us numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 595 - revision v1.06 7.4.8 specification of usb phy 7.4.8.1 usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp-padm| 0.2 v v cm differential common-mode range includes v di range 0.8 2.5 v v se single-ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull-up resistor 1.425 1.575 k ? r pd pull-down resistor 14.25 15.75 k ? v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 ? c in transceiver capacitance pin to gnd 20 pf *driver output resistance doesn?t include series resistor resistance. 7.4.8.2 usb full-speed driver electrical characteristics symbol parameter conditions min. typ. max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 111.11 % 7.4.8.3 usb power dissipation symbol parameter conditions min. typ. max. unit standby 50 ua input mode ua i vddreg (full speed) vddd and vddreg supply current (steady state) output mode ua numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 596 - revision v1.06 8 package dimensions 8.1 100l lqfp (14x14x1.4 mm footprint 2.0mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 25 26 50 51 7 7 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 597 - revision v1.06 8.2 64l lqfp (10x10x1.4mm footprint 2.0 mm) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5 numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 598 - revision v1.06 8.3 48l lqfp (7x7x1.4mm footprint 2.0mm) y seating plane d e e b a2 a1 a 1 12 48 d h e h l1 l c controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13 numicro? nuc100 series technical reference manual publication release date: oct 22, 2010 - 599 - revision v1.06 9 revision history version date page/ chap. description v1.00 march 27, 2010 - preliminary version initial issued v1.01 april 23, 2010 page 529 - 1. correct the error in cbov[1:0] of config0 2. add nuc101 qfn 36-pin parts 3. add current curve in dc characteristics. v1.02 may 5, 2010 - 1. revise nuc101 selection guide. v1.03 june 7, 2010 chap 5.6 cha p 5.8 1. update the section content of i2c serial interface controller. 2. update the section content of real time clock (rtc). v1.04 aug. 23, 2010 page 55 page 575 1. modify pin description 2. modify operation current of dc characteristics v1.05 sep. 14, 2010 page 390 page 375 page 541 1. add rs485 for low density 2. correct the wdt bit length 3. add ebi interface for low density v1.06 dec. 22, 2010 chap 5.10 cha p 5.7.6 - 1. modify timer feature description and add function description 2. modify ccr0 and pier bit description 3. remove nuc101 series numicro? nuc100 series technical reference manual publication release date: dec. 22, 2010 - 600 - revision v1.06 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton. |
Price & Availability of NUC120VE3AN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |